Warning: set_time_limit(): Cannot set time limit in safe mode in /home/www/dynamic/uv.ro/pubory.uv.ro/public_html/pub/index.php on line 526 docs/00index.txt0000755000000000000000000000007611266514557010726 0ustar snesrom.zip SNES ROM information 1.5 - by Damaged Cybernetics docs/dma.txt0000755000000000000000000001270211266514560010211 0ustar From: LAY@uk.tele.nokia.fi To: "Super Famicom Development Group" Subject: RE: Assorted questions... >> 2) I asked a question before about HDMA, and I got replies saying that >> it has something to do with the horizontal interrupt or horizontal >> blank time (I forget which). Later on I saw people talking about >> HDMA "channels". Could someone please tell me what the "channels" >> are used for, or are they another name for a register or a memory >> storage location? It's probably best to start by explaning "normal" DMA. The SNES supports 8 DMA channels which allow data to be copied to VRAM extremely quickly, bypassing the 65c816 processor. Each channel consists of the following registers. Byte $43?0 DMA channel ? control register Byte $43?1 DMA channel ? destination Word $43?2 DMA channel ? source address offset Byte $43?4 DMA channel ? source address bank Word $43?5 DMA channel ? transfer bytes where ? is 0..7 A value of $01 written to the DMA channel control register at $43?0 indicates that we're using "normal" DMA. The graphics register destination is formed by using $21 as the high byte of the address and using the byte specified at $43?1 as the low byte. Hence you can DMA to any of the graphics registers between $2100..$21FF. There is also a DMA control register. Byte $420B DMA control register Here bit 0 enables channel 0, bit 1 enables channel 1 etc... For example, suppose I wanted to copy a 32 x 32 character screen map (ie. $800 bytes) from location $18000 in ROM into location $0000 of VRAM. I could do this using DMA channel 0 with the following code (A is 8-bits, X & Y are 16-bits). ldx.w #$0000 ; set VRAM pointer to $0000 stx $2116 lda #$01 ; control value for "normal" DMA sta $4300 lda #$18 ; dma to $2118 sta $4301 ldx.w #$8000 ; source offset stx $4302 lda #$01 ; source bank sta $4304 ldx.w #$0800 ; number of bytes stx $4305 lda #$01 ; enable DMA channel 0 sta $420B And that's all there is to it. After completion of the last instruction "sta $420B" the $800 bytes at $18000 will have been copied into VRAM at location $0000. HDMA allows you to use any combination of these DMA channels to modify graphics registers just before the start of every horizontal scan line. To use HDMA you have to write a value of $00 or $02 to the DMA channel control register at $43?0 to indicate "horizontal" DMA. Writing $00 indicates a byte is to be DMA'd each scan line, writing $02 indicates a word. The DMA channel destination at $43?1 works just as before with "normal" DMA. The source address offset and bank registers at $43?2 & $43?4 will point to a HDMA table. The transfer bytes register at $43?5 is not used. The format of the HDMA table depends on the value you have written to the DMA channel control register. If you have written $00 then a byte will be written to the selected graphics register each scan line. The table should have the following format. hdma_table Byte n ; number of bytes that follow (7-bit value 0..127) Byte value_1, value_2, value_3 ... value_n Byte n ; number of bytes that follow (7-bit value 0..127) Byte value_1, value_2, value_3 ... value_n . etc . Byte 0 ; ends list The table is made up of a number of entries. The first byte in each entry is a count on the number of bytes that follow. The table is terminated by a 0 entry. If you have written $02 to the DMA channel control register then a word will be written to the selected graphics register each scan line. The table should have the following format. hdma_table Byte n ; # times to repeat next word (7-bit value 0..127) Word value Byte n ; # times to repeat next word (7-bit value 0..127) Word value . etc . Byte 0 ; ends list The table is made up of a number of entries. The first byte of each entry indicates the number of times the following word is to be repeated. The table is terminated by a 0 entry. The only other thing you'll need to know is that there is a HDMA control register. Byte $420C HDMA control register This is the same format as the DMA control register at $420B, ie. bit 0 enables HDMA channel 0, bit 1 enables channel 1 etc... For example, suppose halfway down the screen I want to scroll graphics plane 0 left by 128 pixels. lda #$02 ; word format HDMA (count, word) sta $4300 lda #$0D ; plane 0 x-scroll at $210D sta $4301 ldx.w #hdma_table&$FFFF ; hdma table offset stx $4302 lda #hdma_table/$10000 ; hdma table bank sta $4304 lda #$01 ; enable HDMA channel 0 sta $420c . . . hdma_table dc.b 112 ; for first 112 scan lines dc.w 0 ; set plane 0 x-scroll to 0 dc.b 1 ; on next scan line dc.w 128 ; set plane 0 x-scroll to 128 dc.b 0 You can use HDMA channels in combination, ie. you could use HDMA channel 0 to select a colour register and HDMA channel 1 to write the RGB data for that colour register. I don't have access to any of the official Nintendo documentation so I may not have entirely understood everything about HDMA but this is a much as I've been able to work out. Maybe there are other (H)DMA modes too? I'll should have put a simple HDMA demo with source code on the busop.cit.wayne.edu ftp site (in pub/famidev/incoming/hdmademo.zip). Hope that helps. Paul. docs/famiclr.txt0000755000000000000000000000245411266514561011071 0ustar The Nintendo Super Famicom is capable of displaying 256 colours from a palette of 32,768. These 256 colours are split into 8 palettes of 32 colours each. To change the colours the following needs to be done: Loading the palette control register ($2121) with the colour number you wish to change (0-255, 0=background). Then load the colour into the palette data register first the low 8 bits, followed by the high 7 bits (this gives you the maximum 32768 colours possible $0000-$7fff). Colour data is made up of 3 components (Red,Green,Blue) each of 5 bits (The Amiga uses exactly the same system, but only using 4 bits per component). Saying that, Nintendo being the stupid japanese idiots they are decided that R,G,B wasn't alphabetically correct and so opted to store the bits as B,G,R. 00000 00000 00000 \ / \ / \ / \ / \ / \ / B G R Examples: ~~~~~~~~~ 11111 00000 00000 = $7C00 (Bright Blue) 00000 11111 00000 = $03E0 (Bright Green) 00000 00000 11111 = $001F (Bright Red) 00000 00000 00000 = $0000 (Black) 11111 11111 11111 = $7FFF (White) Easy, isn't it?? (But remember to load the lowest 8 bits first, then the top 7 bits). Starr/QUARTEX docs/famicon.txt0000755000000000000000000005204311266514562011070 0ustar ***************************************************************************** * * * Famicon CPU G65SC802 / G65SC816 Instructionset * * * * Compiled by Carnivore/BeerMacht on 23-Aug-92 using BeerMon V0.43 * * * * FreeWare! * * * ***************************************************************************** >_00060000 e2 30 sep #$30 a,x,y:8bit ;0 >_00060002 69 12 adc #$12 ;i. >_00060004 65 12 adc $12 ;e. >_00060006 75 12 adc $12,x ;u. >_00060008 72 12 adc ($12) ;r. >_0006000a 61 12 adc ($12,x) ;a. >_0006000c 71 12 adc ($12),y ;q. >_0006000e 67 12 adc [$12] ;g. >_00060010 77 12 adc [$12],y ;w. >_00060012 6d 34 12 adc $1234 ;m4. >_00060015 7d 34 12 adc $1234,x ;}4. >_00060018 79 34 12 adc $1234,y ;y4. >_0006001b 6f 56 34 12 adc $123456 ;oV4. >_0006001f 7f 56 34 12 adc $123456,x ;V4. >_00060023 63 12 adc $12,s ;c. >_00060025 73 12 adc ($12,s),y ;s. >_00060027 29 12 and #$12 ;). >_00060029 25 12 and $12 ;%. >_0006002b 35 12 and $12,x ;5. >_0006002d 32 12 and ($12) ;2. >_0006002f 21 12 and ($12,x) ;!. >_00060031 31 12 and ($12),y ;1. >_00060033 27 12 and [$12] ;'. >_00060035 37 12 and [$12],y ;7. >_00060037 2d 34 12 and $1234 ;-4. >_0006003a 3d 34 12 and $1234,x ;=4. >_0006003d 39 34 12 and $1234,y ;94. >_00060040 2f 56 34 12 and $123456 ;/V4. >_00060044 3f 56 34 12 and $123456,x ;?V4. >_00060048 23 12 and $12,s ;#. >_0006004a 33 12 and ($12,s),y ;3. >_0006004c 0a asl a ;. >_0006004d 06 12 asl $12 ;.. >_0006004f 16 12 asl $12,x ;.. >_00060051 0e 34 12 asl $1234 ;.4. >_00060054 1e 34 12 asl $1234,x ;.4. >_00060057 89 12 bit #$12 ;.. >_00060059 24 12 bit $12 ;$. >_0006005b 34 12 bit $12,x ;4. >_0006005d 2c 34 12 bit $1234 ;,4. >_00060060 3c 34 12 bit $1234,x ;<4. >_00060063 c9 12 cmp #$12 ;. >_00060065 c5 12 cmp $12 ;. >_00060067 d5 12 cmp $12,x ;. >_00060069 d2 12 cmp ($12) ;. >_0006006b c1 12 cmp ($12,x) ;. >_0006006d d1 12 cmp ($12),y ;. >_0006006f c7 12 cmp [$12] ;. >_00060071 d7 12 cmp [$12],y ;. >_00060073 cd 34 12 cmp $1234 ;4. >_00060076 dd 34 12 cmp $1234,x ;4. >_00060079 d9 34 12 cmp $1234,y ;4. >_0006007c cf 56 34 12 cmp $123456 ;V4. >_00060080 df 56 34 12 cmp $123456,x ;V4. >_00060084 c3 12 cmp $12,s ;. >_00060086 d3 12 cmp ($12,s),y ;. >_00060088 e0 12 cpx #$12 ;. >_0006008a e4 12 cpx $12 ;. >_0006008c ec 34 12 cpx $1234 ;4. >_0006008f c0 12 cpy #$12 ;. >_00060091 c4 12 cpy $12 ;. >_00060093 cc 34 12 cpy $1234 ;4. >_00060096 3a dec a ;: >_00060097 c6 12 dec $12 ;. >_00060099 d6 12 dec $12,x ;. >_0006009b ce 34 12 dec $1234 ;4. >_0006009e de 34 12 dec $1234,x ;4. >_000600a1 49 12 eor #$12 ;I. >_000600a3 45 12 eor $12 ;E. >_000600a5 55 12 eor $12,x ;U. >_000600a7 52 12 eor ($12) ;R. >_000600a9 41 12 eor ($12,x) ;A. >_000600ab 51 12 eor ($12),y ;Q. >_000600ad 47 12 eor [$12] ;G. >_000600af 57 12 eor [$12],y ;W. >_000600b1 4d 34 12 eor $1234 ;M4. >_000600b4 5d 34 12 eor $1234,x ;]4. >_000600b7 59 34 12 eor $1234,y ;Y4. >_000600ba 4f 56 34 12 eor $123456 ;OV4. >_000600be 5f 56 34 12 eor $123456,x ;_V4. >_000600c2 43 12 eor $12,s ;C. >_000600c4 53 12 eor ($12,s),y ;S. >_000600c6 1a inc a ;. >_000600c7 e6 12 inc $12 ;. >_000600c9 f6 12 inc $12,x ;. >_000600cb ee 34 12 inc $1234 ;4. >_000600ce fe 34 12 inc $1234,x ;4. >_000600d1 a9 12 lda #$12 ;. >_000600d3 a5 12 lda $12 ;. >_000600d5 b5 12 lda $12,x ;. >_000600d7 b2 12 lda ($12) ;. >_000600d9 a1 12 lda ($12,x) ;. >_000600db b1 12 lda ($12),y ;. >_000600dd a7 12 lda [$12] ;. >_000600df b7 12 lda [$12],y ;. >_000600e1 ad 34 12 lda $1234 ;4. >_000600e4 bd 34 12 lda $1234,x ;4. >_000600e7 b9 34 12 lda $1234,y ;4. >_000600ea af 56 34 12 lda $123456 ;V4. >_000600ee bf 56 34 12 lda $123456,x ;V4. >_000600f2 a3 12 lda $12,s ;. >_000600f4 b3 12 lda ($12,s),y ;. >_000600f6 a2 12 ldx #$12 ;. >_000600f8 a6 12 ldx $12 ;. >_000600fa b6 12 ldx $12,y ;. >_000600fc ae 34 12 ldx $1234 ;4. >_000600ff be 34 12 ldx $1234,y ;4. >_00060102 a0 12 ldy #$12 ;. >_00060104 a4 12 ldy $12 ;. >_00060106 b4 12 ldy $12,x ;. >_00060108 ac 34 12 ldy $1234 ;4. >_0006010b bc 34 12 ldy $1234,x ;4. >_0006010e 46 12 lsr $12 ;F. >_00060110 56 12 lsr $12,x ;V. >_00060112 4e 34 12 lsr $1234 ;N4. >_00060115 5e 34 12 lsr $1234,x ;^4. >_00060118 09 12 ora #$12 ;.. >_0006011a 05 12 ora $12 ;.. >_0006011c 15 12 ora $12,x ;.. >_0006011e 12 12 ora ($12) ;.. >_00060120 01 12 ora ($12,x) ;.. >_00060122 11 12 ora ($12),y ;.. >_00060124 07 12 ora [$12] ;.. >_00060126 17 12 ora [$12],y ;.. >_00060128 0d 34 12 ora $1234 ;.4. >_0006012b 1d 34 12 ora $1234,x ;.4. >_0006012e 19 34 12 ora $1234,y ;.4. >_00060131 0f 56 34 12 ora $123456 ;.V4. >_00060135 1f 56 34 12 ora $123456,x ;.V4. >_00060139 03 12 ora $12,s ;.. >_0006013b 13 12 ora ($12,s),y ;.. >_0006013d 2a rol a ;* >_0006013e 26 12 rol $12 ;&. >_00060140 36 12 rol $12,x ;6. >_00060142 2e 34 12 rol $1234 ;.4. >_00060145 3e 34 12 rol $1234,x ;>4. >_00060148 6a ror a ;j >_00060149 66 12 ror $12 ;f. >_0006014b 76 12 ror $12,x ;v. >_0006014d 6e 34 12 ror $1234 ;n4. >_00060150 7e 34 12 ror $1234,x ;~4. >_00060153 e9 12 sbc #$12 ;. >_00060155 e5 12 sbc $12 ;. >_00060157 f5 12 sbc $12,x ;. >_00060159 f2 12 sbc ($12) ;. >_0006015b e1 12 sbc ($12,x) ;. >_0006015d f1 12 sbc ($12),y ;. >_0006015f e7 12 sbc [$12] ;. >_00060161 f7 12 sbc [$12],y ;. >_00060163 ed 34 12 sbc $1234 ;4. >_00060166 fd 34 12 sbc $1234,x ;4. >_00060169 f9 34 12 sbc $1234,y ;4. >_0006016c ef 56 34 12 sbc $123456 ;V4. >_00060170 ff 56 34 12 sbc $123456,x ;V4. >_00060174 e3 12 sbc $12,s ;. >_00060176 f3 12 sbc ($12,s),y ;. >_00060178 85 12 sta $12 ;.. >_0006017a 95 12 sta $12,x ;.. >_0006017c 92 12 sta ($12) ;.. >_0006017e 81 12 sta ($12,x) ;.. >_00060180 91 12 sta ($12),y ;.. >_00060182 87 12 sta [$12] ;.. >_00060184 97 12 sta [$12],y ;.. >_00060186 8d 34 12 sta $1234 ;.4. >_00060189 9d 34 12 sta $1234,x ;.4. >_0006018c 99 34 12 sta $1234,y ;.4. >_0006018f 8f 56 34 12 sta $123456 ;.V4. >_00060193 9f 56 34 12 sta $123456,x ;.V4. >_00060197 83 12 sta $12,s ;.. >_00060199 93 12 sta ($12,s),y ;.. >_0006019b 86 12 stx $12 ;.. >_0006019d 96 12 stx $12,y ;.. >_0006019f 8e 34 12 stx $1234 ;.4. >_000601a2 84 12 sty $12 ;.. >_000601a4 94 12 sty $12,x ;.. >_000601a6 8c 34 12 sty $1234 ;.4. >_000601a9 64 12 stz $12 ;d. >_000601ab 74 12 stz $12,x ;t. >_000601ad 9c 34 12 stz $1234 ;.4. >_000601b0 9e 34 12 stz $1234,x ;.4. >_000601b3 14 12 trb $12 ;.. >_000601b5 1c 34 12 trb $1234 ;.4. >_000601b8 04 12 tsb $12 ;.. >_000601ba 0c 34 12 tsb $1234 ;.4. >_000601bd c2 30 rep #$30 a,x,y:16bit ;0 >_000601bf 69 34 12 adc #$1234 ;i4. >_000601c2 29 34 12 and #$1234 ;)4. >_000601c5 89 34 12 bit #$1234 ;.4. >_000601c8 c9 34 12 cmp #$1234 ;4. >_000601cb e0 34 12 cpx #$1234 ;4. >_000601ce c0 34 12 cpy #$1234 ;4. >_000601d1 49 34 12 eor #$1234 ;I4. >_000601d4 a9 34 12 lda #$1234 ;4. >_000601d7 a2 34 12 ldx #$1234 ;4. >_000601da a0 34 12 ldy #$1234 ;4. >_000601dd 09 34 12 ora #$1234 ;.4. >_000601e0 e9 34 12 sbc #$1234 ;4. >_000601e3 e2 30 sep #$30 a,x,y:8bit ;0 >_000601e5 90 fe bcc $601e5 ;. >_000601e7 b0 fc bcs $601e5 ; >_000601e9 f0 fa beq $601e5 ; >_000601eb 30 f8 bmi $601e5 ;0 >_000601ed d0 f6 bne $601e5 ; >_000601ef 10 f4 bpl $601e5 ;. >_000601f1 80 f2 bra $601e5 ;. >_000601f3 50 f0 bvc $601e5 ;P >_000601f5 70 ee bvs $601e5 ;p >_000601f7 18 clc ;. >_000601f8 d8 cld ; >_000601f9 58 cli ;X >_000601fa b8 clv ; >_000601fb ca dex ; >_000601fc 88 dey ;. >_000601fd e8 inx ; >_000601fe c8 iny ; >_000601ff ea nop ; >_00060200 f4 34 12 pea $1234 ;4. >_00060203 d4 12 pei ($12) ;. >_00060205 62 fd ff per $60205 ;b >_00060208 48 pha ;H >_00060209 8b phb ;. >_0006020a 0b phd ;. >_0006020b 4b phk ;K >_0006020c 08 php ;. >_0006020d da phx ; >_0006020e 5a phy ;Z >_0006020f 68 pla ;h >_00060210 ab plb ; >_00060211 2b pld ;+ >_00060212 28 plp ;( >_00060213 fa plx ; >_00060214 7a ply ;z >_00060215 38 sec ;8 >_00060216 f8 sed ; >_00060217 78 sei ;x >_00060218 aa tax ; >_00060219 a8 tay ; >_0006021a 5b tcd ;[ >_0006021b 7b tdc ;{ >_0006021c 3b tsc ;; >_0006021d ba tsx ; >_0006021e 8a txa ;. >_0006021f 9a txs ;. >_00060220 9b txy ;. >_00060221 98 tya ;. >_00060222 fb xce ; >_00060223 00 12 brk #$12 ;.. >_00060225 82 fd ff brl $60225 ;. >_00060228 02 12 cop #$12 ;.. >_0006022a dc 34 12 jml ($1234) ;4. >_0006022d 4c 34 12 jmp $1234 ;L4. >_00060230 6c 34 12 jmp ($1234) ;l4. >_00060233 7c 34 12 jmp ($1234,x) ;|4. >_00060236 5c 56 34 12 jmp $123456 ;\V4. >_0006023a 22 56 34 12 jsl $123456 ;"V4. >_0006023e 20 34 12 jsr $1234 ; 4. >_00060241 fc 34 12 jsr ($1234,x) ;4. >_00060244 54 34 12 mvn $1234 ;T4. >_00060247 44 34 12 mvp $1234 ;D4. >_0006024a c2 30 rep #$30 a,x,y:16bit ;0 >_0006024c 40 rti ;@ >_0006024d 6b rtl ;k >_0006024e 60 rts ;` >_0006024f e2 30 sep #$30 a,x,y:8bit ;0 >_00060251 db stp ; >_00060252 cb wai ; >_00060253 eb xba ; - EOT - docs/famitec2.txt0000755000000000000000000001345111266514563011147 0ustar Version 1.1 Corrected an error in screen sizes and removed a quesry on sound registers. Corsair + Kari presents the first dox of Fami hardware register locations and brief explanation of them.. If you would like to add any info found in this list please leave a mail message to Corsair or RamRaider on GRAVEYARD BBS +44-91-5160560 or anything to do with the FAMICON/SNES.. We have an INTERNET address if ya want it leave true e-mail! Or better still if ya can get the Programmers handbook (Both) please call and leave mail :) , or even the 100,000 quid SCSI SNASM board for FAMICON development :) Also if you want more info contact us the same way.. We are esp looking for contacts to help get to grips with this new platform everybody welcome! Special greetings to Starr/QUARTEX and any other True Console Dude! coming soon is some sound chip info........ Memory Map ~~~~~~~~~~ Bank Address ~~~~ ~~~~~~~ 00- 0000-1fff Lo RAM (same as at $7e0000-$7e1fff) 7d 2100-2142(?) Videochip Registers 4300-437f DMA Registers 8000-ffff ROM:This contains 32k block of game ROM. So, the games are divided to 32k chunks which locate always at address $8000-$ffff, but in different banks. This means that the first 32k of game is at $008000-$00ffff and next 32k is at $018000-$01ffff etc. 7e 0000-1fff Lo RAM (same as always at $0000-$1fff) \ 2000-ffff RAM \ I'm not sure about } 128k RAM?? 7f 0000-ffff RAM / this RAM / 7f-ff all Not used??? $ffec($fffc) contains reset vector and $ffea($fffa) is NMI vector. The NMI is actually vertical blank interrupt. Video Chip ~~~~~~~~~~ size loc. ~~~~ ~~~~ B 2100 Screen fade x000bbbb x=screen on/off b=brightness(0-f) B 2106 Screen Pixelation xxxxbbbb x=pixel size b=planes to expand B 2107 Plane 0 location in vram xxxxxxab x=address ab=32/64 width xy B 2108 Plane 1 location in vram xxxxxxab as above B 2109 Plane 2 location in vram xxxxxxab as above B 210a Plane 3 location in vram xxxxxxab as above B 210b Tile VRAM address aaaabbbb a=Playfield 0 b=Playfield 1 B 210c Tile VRAM address ccccdddd c=Playfield 2 d=Playfield 3 2B 210d Plane 0 scroll x 8+3 bits (0-7ff) put first 8 bits and then 2B 210e Plane 0 scroll y 8+3 bits (0-7ff) 3 highest bits 2B 210f Plane 1 scroll x as above 2B 2110 Plane 1 scroll y as above 2B 2111 Plane 2 scroll x as above 2B 2112 Plane 2 scroll y as above 2B 2113 Plane 3 scroll x as above 2B 2114 Plane 3 scroll y as above B 2115 Video port control W 2116 Video port address (lo-hi) W 2118 Video port data (lo-hi) (address is incremented by 2) B 2121 Palette color nr B 2122 Palette color data B 212C Playfield Enable xxxxabcd a-d = playfield number.. B 2133 Screen mode 0000ab0c a=Interlace Y b=Overscan c=Interlace X?? 2140-2142 Audio Registers I/O ~~~ W B 420b Start dma (enable bits) bits: 76543210 = dma nr (8 DMA's) R B 4212 Pad ready to be read R W 4218 Pad 0 data 76543210 = A-B-Select-Start-U-D-L-R 4219 76543210 = X-Y-Top Left-Top Right-0000 R W 421a Pad 1 data as above R W 421c Pad 2 data as above R W 421e Pad 3 data as above DMA registers ($4300-$437f) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ B 43X0 DMA control reg??(not sure!) B 43X1 DMA destination (Access only to some of the video chip registers ($2100-$21ff) $18=video port $22=color palette W 43X2 Source address lo-hi 16 lowest bits B 43X4 Source Bank addr. 8 highest bits W 43X5 Transfer size lo-hi X=dma number (0-7) DMA #0= 4300-4305 DMA #1= 4310-4315 ... DMA #7= 4370-4375 Symbols: size: B=byte long 2B=put 2 bytes W=word long R=read only W=write only Screen Details ~~~~~~~~~~~~~~ Famicom Tile format is simple. Each Tile is 4 planes and 8x8 bits. 32 bytes are used per Tile . PLANES 1 & 2 PLANES 3 & 4 byte0 byte1 byte 16 byte 17 byte2 byte3 byte 18 byte 19 byte4 byte5 byte 20 byte 21 ..... ....... byte14 byte15 byte 30 byte 31 Screen Map ~~~~~~~~~~ Famicom can use only Tiles $0-$3ff, max 1024 chars. 16 bits: YX?c ccNN NNNN NNNN fedc ba98 7654 3210 Y = mirror y X = mirror x ?=unknown ccc = palette nr (8 palettes) NN.. = character number Screen Resolution is normally 32x32 chars but only the first 30 y blocks are visible (until scrolled) - 64 bytes / line Screen VRAM Location ~~~~~~~~~~~~~~~~~~~~ Screen Width 32x32 offset for x,y 0,0 = 0 Screen Width 64x32 offset for x,y 0,0 = 0 33,0 = $400 Screen Width 32x64 offset for x,y 0,0 = 0 0,33 = $400 Screen Width 64x64 offset for x,y 0,0 = 0 33,0 = $400 0,33 = $800 33,33 = $c00 As can be seen if a wider mode is selected the extra height/width follow after the main screen in memory. ============================================================================= docs/famitech.txt0000755000000000000000000001304611266514564011236 0ustar ; ; version 1.0 ; Corsair + Kari presents the first doc of Fami hardware register locations and brief explanation of them.. If you would like to add any info found in this list please leave a mail message to Corsair or RamRaider on GRAVEYARD BBS +44-91-5160560 or anything to do with the FAMICON/SNES.. We have an INTERNET address if ya want it leave true e-mail! Or better still if ya can get the Programmers handbook (Both) please call and leave mail :) , or even the 100,000 quid SCSI SNASM board for FAMICON development :) Also if you want more info contact us the same way.. We are esp looking for contacts to help get to grips with this new platform everybody welcome! Special greetings to Starr/QUARTEX and any other True Console Dude! Memory Map ~~~~~~~~~~ Bank Address ~~~~ ~~~~~~~ 00- 0000-1fff Lo RAM (same as at $7e0000-$7e1fff) 7d 2100-2142(?) Videochip Registers 4300-437f DMA Registers 8000-ffff ROM:This contains 32k block of game ROM. So, the games are divided to 32k chunks which locate always at address $8000-$ffff, but in different banks. This means that the first 32k of game is at $008000-$00ffff and next 32k is at $018000-$01ffff etc. 7e 0000-1fff Lo RAM (same as always at $0000-$1fff) \ 2000-ffff RAM \ I'm not sure about } 128k RAM?? 7f 0000-ffff RAM / this RAM / 7f-ff all Not used??? $ffec($fffc) contains reset vector and $ffea($fffa) is NMI vector. The NMI is actually vertical blank interrupt. Video Chip ~~~~~~~~~~ size loc. ~~~~ ~~~~ B 2100 Screen fade x000bbbb x=screen on/off b=brightness(0-f) B 2106 Screen Pixelation xxxxbbbb x=pixel size b=planes to expand B 2107 Plane 0 location in vram xxxxxxab x=address ab=32/64 width xy B 2108 Plane 1 location in vram xxxxxxab as above B 2109 Plane 2 location in vram xxxxxxab as above B 210a Plane 3 location in vram xxxxxxab as above B 210b Tile VRAM address aaaabbbb a=Playfield 0 b=Playfield 1 B 210c Tile VRAM address ccccdddd c=Playfield 2 d=Playfield 3 2B 210d Plane 0 scroll x 8+3 bits (0-7ff) put first 8 bits and then 2B 210e Plane 0 scroll y 8+3 bits (0-7ff) 3 highest bits 2B 210f Plane 1 scroll x as above 2B 2110 Plane 1 scroll y as above 2B 2111 Plane 2 scroll x as above 2B 2112 Plane 2 scroll y as above 2B 2113 Plane 3 scroll x as above 2B 2114 Plane 3 scroll y as above B 2115 Video port control W 2116 Video port address (lo-hi) W 2118 Video port data (lo-hi) (address is incremented by 2) B 2121 Palette color nr B 2122 Palette color data B 212C Playfield Enable xxxxabcd a-d = playfield number.. B 2133 Screen mode 0000ab0c a=Interlace Y b=Overscan c=Interlace X?? 2140-2142 Audio Registers???? I/O ~~~ W B 420b Start dma (enable bits) bits: 76543210 = dma nr (8 DMA's) R B 4212 Pad ready to be read R W 4218 Pad 0 data 76543210 = A-B-Select-Start-U-D-L-R 4219 76543210 = X-Y-Top Left-Top Right-0000 R W 421a Pad 1 data as above R W 421c Pad 2 data as above R W 421e Pad 3 data as above DMA registers ($4300-$437f) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ B 43X0 DMA control reg??(not sure!) B 43X1 DMA destination (Access only to some of the video chip registers ($2100-$21ff) $18=video port $22=color palette W 43X2 Source address lo-hi 16 lowest bits B 43X4 Source Bank addr. 8 highest bits W 43X5 Transfer size lo-hi X=dma number (0-7) DMA #0= 4300-4305 DMA #1= 4310-4315 ... DMA #7= 4370-4375 Symbols: size: B=byte long 2B=put 2 bytes W=word long R=read only W=write only Screen Details ~~~~~~~~~~~~~~ Famicom Tile format is simple. Each Tile is 4 planes and 8x8 bits. 32 bytes are used per Tile . PLANES 1 & 2 PLANES 3 & 4 byte0 byte1 byte 16 byte 17 byte2 byte3 byte 18 byte 19 byte4 byte5 byte 20 byte 21 ..... ....... byte14 byte15 byte 30 byte 31 Screen Map ~~~~~~~~~~ Famicom can use only Tiles $0-$3ff, max 1024 chars. 16 bits: YX?c ccNN NNNN NNNN fedc ba98 7654 3210 Y = mirror y X = mirror x ?=unknown ccc = palette nr (8 palettes) NN.. = character number Screen Resolution is normally 32x30 - 64 bytes / line Screen VRAM Location ~~~~~~~~~~~~~~~~~~~~ Screen Width 32x32 offset for x,y 0,0 = 0 Screen Width 64x32 offset for x,y 0,0 = 0 33,0 = $400 Screen Width 32x60 offset for x,y 0,0 = 0 0,31 = $400 Screen Width 64x60 offset for x,y 0,0 = 0 33,0 = $400 0,31 = $800 33,31 = $c00 As can be seen if a wider mode is selected the extra height/width follow after the main screen in memory. docs/faq.txt0000755000000000000000000001106611266514565010226 0ustar SFDG FAQ - Super Famicom Development Group Frequently Asked Questions ~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ By Carl Mueller: carl@busop.cit.wayne.edu SFDG mailer: listserv@busop.cit.wayne.edu (e-mail msg body: HELP) ----------------------------------------------------------------------------- Q. What exactly is the Super Famicom? A. The Super Famicom is the Japanese version of the American SNES (Super Nintendo Entertainment System). As far as hardware goes, they are generally the same and play the same games (SF games can be played on the SNES and vice versa). The Super Famicom however has a different appearance than the SNES, but other than cosmetic differences, they are virtually the same system. ----------------------------------------------------------------------------- Q. What exactly do people use to develope games on the SNES? A. _Professional_ developers, to my knowledge, use a PC and a special 65816 assembler called SNASM which assembles and allows debugging of 65816 code, also included is a device which (I believe) plugs into the SNES and you download code from your PC to the SNES through a SCSI interface. This developers kit is available through Nintendo, but to my knowledge is *extremely* expensive (say around $5000), and Nintendo won't sell it to you unless you belong to a gaming company. ----------------------------------------------------------------------------- Q. What about the demos I've seen floating about, how were those made? A. There are also console "backup" devices like the Super Magicom (SNES/ Super Famicom backup), Super MagicDrive (Sega Genesis backup), and MultiGame Hunter (Genesis and SNES backup) to name a few. People download their own code to these devices using 65816 cross assemblers (apparently availabe to most major platforms), and the SNES runs it. You have to have a pretty good knowledge of the SNES hardware, and of course be an expert 65816 assembler. ----------------------------------------------------------------------------- Q. Where can I get some files which explain the technicial details of the SNES, like memory locations and such? A. An FTP site is available (run by me). ftp busop.cit.wayne.edu. Development files should be located in \sys\pub\famidev. Also, you should be able to find utilities such as assemblers and disassemblers. ----------------------------------------------------------------------------- Q. What the heck is an 65816 ? A. It's a microprocessor made by Western Design which is a basically a souped up 16-bit version of the 6502 (used in older computers like the Commodore 64, etc) and is currently (and probably for enternity) only used in the Apple IIgs system, and of course the SNES/Super Famicom systems. It has 16-bit internal registers and an 8-bit bus. ----------------------------------------------------------------------------- Q. How do I start working for Nintendo, then ? A. Probably the best way to land a job programming for the SNES would be to prove yourself an 65816 expert, and send them a demo of a game written perferably on a DIFFERENT platform (say like the Apple IIgs might be a good computer to show a demo on), Nintendo may not like the fact that you've been coding on their system without any licenses. Or, you can try to get a job at a company that produces SNES games by showing them your game, and getting them to LEGALLY license it. ---------------------------------------------------------------------------- Q. Where do I get a copy of this "Developers Manual" everyone seems to be talking about? A. You don't. Nintendo distributes their developers manual only to licensed game programmers and is apparently very strict about it being copied or information being let out from it. Plus, if you paid $5,000 for a developers kit, would you be so quick to send out copies of the manual? ----------------------------------------------------------------------------- Q. Can I talk about stupid stuff that has nothing to do with SNES development on this mail group? A. No. ----------------------------------------------------------------------------- Well, that's it so far. I may not be the best person to write this FAQ, but so far I'm the only one who has been willing to do it. If you wish to make modifications, let me know. Your free to make additions/modifcations to this document. Just send the revised document to my mail box and I will replace this one. carl@busop.cit.wayne.edu docs/fastrom.txt0000755000000000000000000000400011266514566011121 0ustar From: LAY@uk.tele.nokia.fi To: "Super Famicom Development Group" Subject: The need for speed revisited... Date: Wed, 16 Feb 1994 11:00:49 GMT I unsubscribed from this mailing list after my suggestion that maybe the processor would run faster when executing from RAM brought responses such as "if you want something to run that fast you should use a PC" which quickly turned into a whole barrage of "my Amiga is faster than your PC" mails. Just the sort of comments I was hoping to get from this mailing list... )-: However I'm changing jobs and I don't know whether I'll have internet access at my new job, so I'd better make the most of it... So, for anyone like myself who wants to get the most out of their SNES I thought I'd let you know that I've managed to run the program in FASTROM which has resulted in a 33% speed improvement - the 65816 runs at 3.58Mhz rather than 2.68Mhz. This is possible because the ROMs have a faster access time - hence the reason I thought it may be possible with RAM which typically has faster access times than ROM. So how's it done? The SNES lets you access ROM through bank $00 onwards and bank $80 onwards such that locations $008000 and $808000, $008001 and $808001, $008002 and $808002 etc... all access the same locations. When accessing bank $00 onwards the 65816 runs at 2.68Mhz. However, when accessing bank $80 onwards the 65816 can run at 2.68Mhz or 3.58Mhz depending on how you set bit 0 of $420D. So all you have to do is assemble your program so that it starts at $808000, make sure you set the programming and data banks to $80 (K and D) and set bit 0 of $420D. You'll also need to mask off the bank part of the run/reset vector and vertical blank interrupt locations. Paul. PS. I also see that the source code for an early version of my GIF2SNES program has made it onto the ftp site by a somewhat indirect route (UK->NZ->AUS->USA). If someone wanted this source code let me know and I'll post the latest fully optimising version. docs/index.html0000755000000000000000000001022711277647532010714 0ustar Index of /docs
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Index of /docs

Last Updated: Thirsday, April 8th, 2004

File name Size Last update Description
[..]<DIR>4/8/2004, 0:27Parent directory
descript.ion8124/8/2004, 0:33description file
dma.txt5,57010/12/1995, 0:0Assorted questions...
famiclr.txt1,32410/12/1995, 0:0Famicom RGB
famicon.txt21,5398/23/1992, 0:0Famicon Instructionset
famitec2.txt5,92910/12/1995, 0:0Fami hardware 1.1
famitech.txt5,67010/12/1995, 0:0Fami hardware 1.0
faq.txt4,66210/12/1995, 0:0SFDG FAQ
fastrom.txt2,04810/12/1995, 0:0speed revisited...
ips.doc65710/12/1995, 0:0About IPS
mult.txt1,57910/12/1995, 0:0Multiplying/Dividing?
ram.txt1,88710/9/1993, 0:0some programming questions
screen.txt7,2742/28/1993, 0:0SNES GRAPHICS INFO FILE V1.0 By DAX on 28/2/93
sndoc230.lzh16162910/12/1995, 0:0SNES Doc v2.30: by Yoshi
snes.doc35,84010/12/1995, 0:0SNES Doc v1.3: by Yoshi
snesmap2.txt42,35210/12/1995, 0:0Init Display
snesrom.pin1,18710/12/1995, 0:0snes carts pinout
snesrom.zip4,61210/12/1995, 0:0SNES ROM information 1.5 - by Damaged Cybernetics
spc-700.doc69,7934/8/2004, 0:22tehnical document v1.02
spc.txt1,97010/12/1995, 0:0spc header block
spc2.txt2,75310/12/1995, 0:0spc sample source
spc_file_format.txt4,4674/6/2004, 19:0from an SNESAmp tutorial?
spcTodo.txt92,6986/6/1997, 0:27APU MANUAL
tasm700.zip4,9557/30/1996, 0:12SPC700 table
techspec.txt5,66510/12/1995, 0:0Fami hardware v1.0

There are 24 files and 1 directories
for a total of 486872 bytes. docs/ips.doc0000755000000000000000000000122111266514570010164 0ustar Since I couldn't find any infos on IPS formats i hacked around it for like 10 minutes and came up with this. Format of an IPS (International Patching System) MAJIC : 5 chars = "PATCH" Address : 3 chars patch size : 2 bytes bytes to byte : ? char (size of the patch size) .. if more than one area to patch, start at Address again and follow thru EOF : 3 chars = "EOF" PATCHaaappb?aaappb?EOF <-- ips patch with 2 chunks Later Mind Rape Greets go to Cynix, Sir_Jinx/Censor, c0ke KiD, Ntt, Rom Burner, Sector Slayer/Spectrum, bri_acid, Mytle_, SiCKMAN, dorkwad, goose, and all c00l snes coders docs/mult.txt0000755000000000000000000000305311266514571010432 0ustar From: vic@physci.psu.edu (Vic Ricker) To: "Super Famicom Development Group" Subject: Re: Multiplying/Dividing? Date: Sun, 26 Dec 93 16:29:09 EST Take a look at this: Address: $4202/$4203 Name: WRMPYA/WRMPYB Description: Multiplier and multiplicand D7 D6 D5 D4 D3 D2 D1 D0 | MULTIPLICAND-A | $4202 |_______________________________________| D7 D6 D5 D4 D3 D2 D1 D0 | MULTIPLIER-B | $4203 |_______________________________________| These registers perform absolute multiplication by multiplying multiplicand A by multiplier B and return product C which can be read from $4216/$4217 RDMPY. Set register A, then B. After the B register is set, it will take 8 machine cycles for the multiplication to be completed. * The A register will not be destroyed by the multiplication process. ^^^ does not refer to the accumulator. it means the multiplicand Also, there is 8/16 multiply that shares the mode 7 matrix registers: set 16 bit multiplier to $211b and 8 bit multiplicand to $211c the 24 bit product will be placed in $2134-$2136. The shift-add routine is a great way to multiply. I'm suprised that so many so-called assembly programmers don't know how to do it. Regardless of how fast it is, the hardware stuff blows it away. There is also a hardware divide: $4204/4205 is the 16 bit dividend, $4206 is the 8bit divisor, the quotient will be put in $4214, and the remainder in $4216/4217. ANy questions, lemme know. docs/ram.txt0000755000000000000000000000353711266514572010240 0ustar From: vic@physci.psu.edu (Vic Ricker) To: "Super Famicom Development Group" Subject: Re: some programming questions Date: Tue, 9 Nov 93 20:20:35 EST >Hi Folks. >I need help with a few SNES programming questions... >(1) Can anyone tell me how to make noises come out of my SNES? Insert your favorite cart, power up the TV, switch the snes power to ON.. :-) >(3) Is the sprite position table held in RAM or VRAM? And how > do the 5 address bits in $2101 relate to this location? The sprite images are stored in VRAM. The palettes for the sprites are stored in CGRAM. The coordinates and char attributes are stored in OAM. The format of each OBJ is: OBJ H position: 8 bits OBJ V position: 8 bits V flip: 1 bit H flip: 1 bit OBJ priority: 2 bits color palette: 3 bits character name: 9 bits there are 128 of these in sequence making 512 bytes then 32 bytes follow in the format: size: 1 bit x msb: 1 bit there are 128 of these (one for every OBJ) making 32 more bytes. $2101 is OBJSEL it chooses the size of sprites to use and also sets the address of the images in VRAM. the top 3 bits chose the size: 000 means 8x8 and 16x16 sprites 001 8x8 and 32x32 010 8x8 and 64x64 011 16x16 and 32x32 100 16x16 and 64x64 101 32x32 and 64x64 the other bits are the address in vram of the sprite images. $2102-$2103 is OAMADDL/H the lower 9 bits are the address for accessing the OAM. (like $2116 for VRAM) the high bit (15) enables priority rotation (causes OBJ's to change priority as to keep them from disappearing totally when time out and range over occur.) $2104 is OAMDATA it is the write register for the OAM. (like $2118-$2119 for VRAM) $2138 is *OAMDATA it is the read register for the OAM. Hope this gives you enough to play with. Most is from memory, I hope its all correct. :-) Lemme know if you have questions. docs/screen.txt0000755000000000000000000001615211266514573010736 0ustar SNES GRAPHICS INFO FILE V1.0 ---------------------------- By DAX on 28/2/93 This is a short text file on how the data for the gfx on the SNES are set up.. Everything is based around an 8x8 pixel 'Tile' and thinking in terms of tiles makes the whole thing a lot easier. 4 Colour mode - 2 Bitplanes --------------------------- If you split the screen into 8x8 pixel tiles, the order of the graphics data is tile 0,1,2,3,4 etc.(with tile 0 being the first, and 1 being the one on the right of it.) Then for each tile, the data is stored as shown below. 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17 Each number representing one pixel in 20 21 22 23 24 25 26 27 the 8x8 tile. 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 60 61 62 63 64 65 66 67 70 71 72 73 74 75 76 77 The data is stored in the SNES binary in the following format. Bitplane 0 .. Line 00-07 (One Byte) Line 10-17 Line 20-27 Line 30-37 Line 40-47 Line 50-57 Line 60-67 Line 70-77 then Bitplane 1 .. Line 00-07 Line 10-17 Line 20-27 Line 30-37 Line 40-47 Line 50-57 Line 60-67 Line 70-77 then comes the data for the next tile (the one on the right).etc. 16 Colour - 4 Bitplanes ----------------------- The data for this mode is stored in the same format, with one main change. The data is stored in the format Bitplane 0 .. Line 00-07 | Line 70-77 Bitplane 1 .. Line 00-07 | Line 70-77 Bitplane 2 .. Line 00-07 | Line 70-77 Bitplane 3 .. Line 00-07 | Line 70-77 then the data for the next tile. 256 Colour - 8 Bitplanes ------------------------ This is simply an expansion of the 4 and 16 colour modes. Bitplane 0 .. Line 00-07 | Line 70-77 Bitplane 1 .. Line 00-07 | Line 70-77 Bitplane 2 .. Line 00-07 | Line 70-77 Bitplane 3 .. Line 00-07 | Line 70-77 Bitplane 4 .. Line 00-07 | Line 70-77 Bitplane 5 .. Line 00-07 | Line 70-77 Bitplane 6 .. Line 00-07 | Line 70-77 Bitplane 7 .. Line 00-07 | Line 70-77 then the data for the next tile. 256 Colours - Mode 7 format --------------------------- This has some very major differences to the other graphics data formats there are two mode7 modes, normal and EXTBG, the data is stored in the same way in both, apart from in EXTBG the Bitplane 7 value will be a priority bit for the pixel, which cuts the colours down to 128. Each byte of 'graphics data' is actually the colour value for that pixel on the screen, so if the value is 64, then the colour of that pixel will be the contents of colour register 64. The data is stored in VRAM differently to the other modes, with the tile numbers, and the graphics data 'interleaved', starting at $0000 in VRAM, with alternate bytes containing one byte of tile, one byte of gfx - this is shown below. Word of VRAM. HI LO Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 content |------------------------------||------------------------------| Graphics data(CHAR DATA) Tile number(NAME) Because of the storing of 16 bit data in reverse format (LO-HI) this means that if you set the VRAM addr to $0.the first byte written should be the tile name for that position on screen and the second byte should be the first byte of the Mode7 graphics data.if the VRAM addr is set to $1 the first byte written will be the tile name for that position on scr, and the second byte should be the second byte of the mode7 graphics data. ETC In mode7 you can only have a maximum of 256 tiles, because of the fact that the mode7 data only takes up the first half of VRAM(32k) you can only have 16k of graphics data which is 256 tiles of 8x8 with 256 colours. This is quite a limitation, but can be used quite effectively. The tile numbers are stored in a format according to a 128x128 tile screen so tile 128($80) would be the tile below 0($0) on the screen, and so on. so VRAM addr $0 is the top left tile, and $1 is the one on the right of it $80 is the one on the left side, one row down. the graphics data is stored based on an 8x8 tile again. but slightly different. Each byte(pixel) is stored so... Bit number Contents 0 Bitplane 0 pixel value 1 Bitplane 1 pixel value 2 Bitplane 2 pixel value 3 Bitplane 3 pixel value 4 Bitplane 4 pixel value 5 Bitplane 5 pixel value 6 Bitplane 6 pixel value 7 Bitplane 7 pixel value / (EXTBG mode - Priority value) The data is then stored in the sequence 00,01,02,03,04,05,06,07 10,11,12,13,14,15,16,16 (Look at diagram at start of file | | | for explanation) 70,71,72,73,74,75,76,77 with one byte for each position(pixel), according to the 8x8 tile format, with one tile after another. --------------------------------------------------------------------------- I hope this text file helps those of you having trouble converting graphics for use on the SNES, I have been asked a few times recently for this info so I decided to type up this short text file on it. Hopefully it should explain it! If you have any further questions contact :- Dax or Corsair On the following BBS's The Graveyard +44 (0)91 516 0560 Treasure Island +44 (0)992 451191 (Coders Conf) The Fun House +44 (0)81 443 3174 (Coders Conf) Quick hellos to everyone who I know as I cannot be bothered to type out a list. docs/snes.doc0000755000000000000000000010600011266514574010346 0ustar =-=-= SNES Documentation v1.3: Written by Yoshi of Digital Exodus. =-=-= 1) Memory Map. i) "Main" memory map. ii) Additional info. 2) SNES Color explaination. 3) SNES DMA Memory Map and explaination. 4) SNES Graphics (tiles) explaination. 5) SNES Screen mode definitions. 6) SNES OAM/Sprite explaination. 7) Magicom Disk registers and Memory controller locations. 69) About the author... FF) Greetings, Thanx, etc... =-=-= 1) Memory Map. i) "Main" memory map. ----------- Just so you know... the R and/or W's on the left side before the memory location mean [R]eadable and/or [W]riteable. I don't know what happens if you try to read from the write-only registers: I think you get bogus data, but that's about it. ----------- W |$2100: Screen display register. x000bbbb x: 0 = Screen on. 1 = Screen off. bbbb: 0-$F = Brightness of screen. *** If you increment $2100 so the register goes up to $xF (x being whatever), you can make the screen "fade in". Make -SURE- you do this only during the VBlank period! If you don't, the screen goes totally wacko! The 'GS programmers like myself call it "Syncing to the VBL". ----------- W |$2101: OAM (Sprite) sizes. sssnnbbb s: Size. n: Name selection (upper 4k word address). b: Base selection (8k word segment address). *** The sizes are defined as follows: 000: 8x8 or 16x16 001: 8x8 or 32x32 *** I've never used this register, nor sprites. Check Section 6 for information which was not done by me: If you understand it better than I do, good deal. ----------- W |$2102: Address of OAM (Sprites). ???????? | ???????? *** This register i've never used. All I know is that it's a -WORD- in length, not a byte. ----------- W |$2104: Data for OAM (Sprites). ???????? *** I've never used this register. It's like $210D: You have to store a value in it twice. ----------- W |$2105: Screen mode. abcdfeee a: Plane 3 tile size. b: Plane 2 tile size. c: Plane 1 tile size. d: Plane 0 tile size. 0 = 8x8 tiles. 1 = 16x16 tiles. e: MODE definition. f: Make Plane 2 take highest priority. ----------- W |$2106: Screen pixelation (aka. MOSAIC) register. xxxxabcd x: 0-$F = Pixel size. a: Affect plane 3. b: Affect plane 2. c: Affect plane 1. d: Affect plane 0. *** Just like $2100, this only works during VBlank. I recommend you setup what planes you want to affect at the start of the program, then to make them change, do the following: LDA #$03 ; Affect planes 0 and 1. STA TempReg1 STA $2106 JSR WaitVBlank LDA TempReg1 Loop STA $2106 CLC ADC #$10 CMP #$F3 BNE Loop ----------- W |$2107: Plane 0 VRAM location register. xxxxxxab x: Address of VRAM location. ab: Virtual screen size selection. *** The virtual screen size dealy goes like this: 32x32 to 32x64 to 64x32 to 64x64. Visually, you only see 32x32(x25) at once unless you change the ACTUAL screen size. *** The way I use this register is pretty simple. Lets say the VRAM is in $2000... Therefore, we'd go like this: LDA #$20 STA $2107 ----------- W |$2108: Plane 1 VRAM location register. W |$2109: Plane 2 VRAM location register. W |$210A: Plane 3 VRAM location register. *** All of these follow the same definition as $2107. ----------- W |$210B: Tile VRAM location register. aaaabbbb a: Location of tiles for Plane 1. b: Location of tiles for Plane 0. *** The way you use this register is fairly neat. Since you only have a nybble to work with (which ranges from $0-F only) your Tile location can only be $0000 to $F000. You can't have an address such as $5F91 or $1C4A which holds your tile data. You just can't have it. :-) ----------- W |$210C: Tile VRAM location register. ccccdddd c: Location of tiles for Plane 3. d: Location of tiles for Plane 2. *** Same stats for $210B go for this one; 'cept the plane registers are different. ----------- W |$210D: Plane 0 X-scroll register. *** This register is really funky. You have to write to it twice in a row (each piece of data being 1 byte). The register is setup as the following: - You store the first 8 bits (the first byte) which ranges from $00 to $FF. After you store this value, you have to store the next 3 bits in the same register. *** The following code demonstrates how to move plane 0 left: LDA Plane0X DEC STA Plane0X STA $210D STZ $210D If you make that into a loop by itself, the result is the plane keeps scrolling left forever; it even wraps around back to the start. *** Note: I've been told this is a nasty way to do it because MODE 7 uses 13 bits of the above, while the rest use 10. I'm not taking care of the MSB. :-( ----------- W |$210E: Plane 0 Y-Scroll register. W |$210F: Plane 1 X-Scroll register. W |$2110: Plane 1 Y-Scroll register. W |$2111: Plane 2 X-Scroll register. W |$2112: Plane 2 Y-Scroll register. W |$2113: Plane 3 X-Scroll register. W |$2114: Plane 3 Y-Scroll register. *** All of these follow the same definition as $210D. ----------- W |$2115: Video port control. *** If you store the following listed values in this register, the following happens: $80: H/L increment which determines if the address will be incremented after it reads/writes to/from $2118 and $2139, or $2119 and $213A. W |$2116: Video port address. *** 16 bit VRAM address. $2117: Video port address (continued, due to 16 bits). W |$2118: Video port data. *** Data register for writing VRAM data. $2119: Video port data. *** Same as above. ----------- W |$211A: MODE 7 Information register. xy????ab a: Horizontal or Vertical flip. b: Horizontal or Vertical flip. x: Landscape repeat type. y: Landscape repeat type. *** I have not the SLIGHTEST idea what the hell the original author means by this. If someone can explain it, tell me. ----------- W |$211B: COS (COSIN) rotate angle / X Expansion. W |$211C: SIN (SIN) rotate angle / X Expansion. W |$211D: SIN (SIN) rotate angle / Y Expansion. W |$211E: COS (COSIN) rotate angle / Y Expansion. W |$211F: 13 bit address for the center of Rotate X. W |$2120: 13 bit address for the center of Rotate Y. *** All above things i've never used, nor do I have any explainations on them. Use them at your own risk, or until I get info on 'em. *** $211F and $2120 are like $210D: You have to write a byte to them twice. ----------- W |$2121: Color # (or pallete) selection register. xxxxxxxx x: Color # ($00-$FF). *** This register is probably one of the most simple registers I know of to use. You simply store the # of the color you want to modify before writing to $2122. This register is autoincrementing, so you don't have to "LDA #$01, STA $2121, LDA #$02, STA $2121, LDA #$03..." and so on... Code is as follows: STZ $2121 ; Start at color 0. STZ $2122 ; Color #0 = 00 00 STZ $2122 LDA #$FF ; Color #1 = 7F FF (white). STA $2122 LDA #$7F STA $2122 LDA #$1F ; Color #2 = 00 1F (red). STA $2122 STZ $2122 ----------- W |$2122: Color data register. xxxxxxxx x: Value of color. *** Color on the SNES is trippy; it's 15 bit. Check Section 2 on how the SNES colors are setup. Some example code I listed for $2121... Anyways, this register is like $210D (plane X-scroll) and those types: You have to store the value in it twice. For instance: If you wanted the color white (which is $7FFF in SNES-color), you would have to do the following: LDA [whatever color #] STA $2121 LDA #$FF ; We first store the "lower half" STA $2122 LDA #$7F ; Then the upper... STA $2122 It's really not that hard, but it'll take some getting used to :-) Remember, check Section 2 on how the SNES does it's color, and for tile-setup, check Section 4. ----------- W |$212C: Playfield/Sprite-enable register. abcdefgh a: Plane 3 enable (for Sprites). b: Plane 2 enable (for Sprites). c: Plane 1 enable (for Sprites). d: Plane 0 enable (for Sprites). e: Enable plane 3. f: Enable plane 2. g: Enable plane 1. h: Enable plane 0. *** This register allows you to enable which planes you want to put sprites on (to move or etc.) and to scroll, or other neato things. If you wanna use all 4 planes, but no sprites, shove $0F into this register. If you want to use all the planes, but want sprites on planes 1 and 3, you would shove $AF into this register. It's very easy to do. ----------- W |$2133: Screen mode register. ????ab?c a: Interlace Y. b: Overscan. c: Interlace X. *** To be blatently honest, I have -NO IDEA- what this register does; I don't understand what Corsair & Dax meant by Interlace and Overscan. If someone can explain this register to me, i'd be very grateful :-). ----------- R |$2139: VRAM port data (reading). $213A: " " ----------- ?? |$2140 *** These are the audio registers. 'never used 'em. ?? |$2141 Try shoving data into them; who knows, if you get ?? |$2142 music sometime, then you know you're on the right ?? |$2143 track. :-) ----------- ?? |$4200: Counter Enable. ??yx???a a: Joypad-read Enable (1 = Readable). x: Horizontal Counter Enable. y: Vertical Counter Enable. ----------- ?? |$4201: 8 bit parallel data. *** This is the expansion bus for the Famicom. ----------- RW |$420B: DMA enable register. abcdefgh a: DMA #7. b: DMA #6. c: DMA #5. d: DMA #4. e: DMA #3. f: DMA #2. g: DMA #1. h: DMA #0. *** I've personally never used DMA for anything. I hope someone out there has, and can tell me how to use it. :-) ----------- ?? |$420D: Memory select. ???????x x: Fast/Normal ROM flip. 0 = Normal. 1 = Fast. ----------- R |$4210: VBL register. x??????? x: VBlank period 1 = On. 0 = Off. *** This is probably the most important register you should work with. Without it, you die, and other things happen. :-) The following routine allows you to sync to the VBL/wait for the VBL to pass by so you can do your work: - LDA $4210 AND #$80 BEQ - LDA $4210 From a programmers' standpoint, the following code should do the EXACT SAME as the above, but faster. NOTE thou, that it doesn't. I think the timing is off, that's why it doesn't work right. But, here-goes: - LDA $4210 BPL - LDA $4210 ----------- ?? |$4211: ?????. x??????? x: IRQ Enable flag (1: Enabled). *** I don't even know the DESCRIPTION of the reg- ister! :-) ----------- RW |$4212: Joypad-ready register. ???????x x: Ready-state bit (1: Ready). *** I'm not sure how this register is setup; all I know is how to use it. Code is as follows: PadLoop LDA $4212 AND #$01 BNE PadLoop This waits for the joypad to become ready to read. ----------- RW |$4218: Joypad #0 register (1 out of 2). abcd0000 a: 0 = A button not pressed. 1 = A button pressed. b: 0 = X button not pressed. 1 = X button pressed. c: 0 = Top-left button not pressed. 1 = Top-left button pressed. d: 0 = Top-right button not pressed. 1 = Top-right button pressed. *** These are self-explainitory. To find out the status of each bit, just AND #$ for that bit... The code for checking is the following: LDA $4218 AND #$80 ; Is the A button pressed? BNE YesA ; Button pressed (bit is 1). LDA $4218 AND #$40 ; Is button X pressed? BNE YesX ; Button pressed (bit is 1). LDA $4218 AND #$10 ; Is the top-right button pressed? BNE YesTopR ; Button pressed (bit is 1). ...and so on. It's very simple. *** Note: The Corsair & Dax document was -WRONG-. It took me a good hour or two to find this out, so I decided i'd better write down the CORRECT way to do things). ----------- RW |$4219: Joypad #0 register (2 out of 2). abcdefgh a: 0 = B button not pressed. 1 = B button pressed. b: 0 = Y button not pressed. 1 = Y button pressed. c: 0 = Select button not pressed. 1 = Select button pressed. d: 0 = Start button not pressed. 1 = Start button pressed. e: 0 = Up not pressed. 1 = Up pressed. f: 0 = Down not pressed. 1 = Down pressed. g: 0 = Left not pressed. 1 = Left pressed. h: 0 = Right not pressed. 1 = Right pressed. *** Same as $4218... Some demo code follows: LDA $4219 AND #$80 ; Is the B button pressed? BNE YesB ; Button pressed (bit is 1). LDA $4219 AND #$04 ; Is Down pressed? BNE YesDown ; Button pressed (bit is 1). LDA $4219 AND #$02 ; Is Left pressed? BNE YesLeft ; Button pressed (bit is 1). ----------- RW |$421A: Joypad #1 register (1 out of 2). RW |$421B: Joypad #1 register (2 out of 2). RW |$421C: Joypad #2 register (1 out of 2). RW |$421D: Joypad #2 register (2 out of 2). RW |$421E: Joypad #3 register (2 out of 2). RW |$421F: Joypad #3 register (2 out of 2). *** Setup is the same as $4218 and $4219. =-=-= 1) Memory Map ii) Additional info. ----------- RW |$FFC0: Cartridge title. RW |$FFD6: ROM/RAM Info on cart.. RW |$FFD7: ROM Size. RW |$FFD8: RAM Size. RW |$FFD9: Maker ID Code. RW |$FFDB: Version #. RW |$FFDC: Checksum complement. RW |$FFDE: Checksum. RW |$FFEA: NMI vector/VBL Interrupt. RW |$FFEC: Reset vector. *** With SMC (Magicom) files the offset is $7e00 less than above. *** I've never actually used this information before: This could be SMC header only; but then why would there be memory locations for such? Strange. I'll leave the information I put in up to SNESASM v1.05. I use the psuedo-ops NAM, VER, and other things. =-=-= 2) SNES Color explaination. ----------- Oh BOY! So you're interested in finding out how the SNES does it's color (via $2122), right? Well here ya go... The SNES has a strange way of doing color (atleast that i've seen in my lifetime). Color is 15 bit; each "RGB" value (red, green, and blue) has 5 bits a piece. When it comes to putting data into $2122, the format (in binary) is the following (I put them into each byte): 0bbbbbgg gggrrrrr | |_ Someone needs to tell me what this bit -REALLY- is. I've just been told to set it to 0... We guess that the Japanese didn't like the idea of putting them in the "standard" order of R, G, then B: but instead wanted them in alphabetical order. Silly! :-). The way -I- do my color conversions is on a calculator... Just plug in the bits you want to set in binary, then let the calc. convert it into hexadecimal. It's pretty easy; or you can be a Studly Programmer (hehehe) and do it in your head. A quick color chart: $7FFF: White (0111 1111 1111 1111) $001F: Red (0000 0000 0001 1111) $03E0: Green (0000 0011 1110 0000) $7C00: Blue (0111 1100 0000 0000) $7C1F: Purple (0111 1100 0001 1111) $7FE0: Aqua (0111 1111 1110 0000) $03FF: Yellow (0000 0011 1111 1111); Well there you have it. It's pretty simple after you get the hang of it; when using the SNES, you get REALLY good with binary math: You'll find this out after working with the machine for awhile. =-=-= 3) DMA Memory Map and explaination. ----------- ?? |$43x0: DMA Control register (??? Not sure ???). W |$43x1: DMA Destination register. $18 = Video Port access. $22 = Color pallete access. *** This gives access to only some of the video chip. registers. Hell if I know which ones. ----------- W |$43x2: Source address. *** THIS REGISTER IS A WORD IN LENGTH *** *** The document I have says: "lo-hi 16 lowest bits". Who knows... ----------- W |$43x4: Source bank address. *** The document I have says: "8 highest bits". ----------- W |$43x5: Transfer size register. *** Same as above: "lo-hi". ----------- All the "x"s represent the DMA # (ranging from 0 to 7). DMA #0: $4300-$4305. DMA #1: $4310-$4315. ...... DMA #7: $4370-$4375. =-=-= 4) SNES Graphics (tiles) explaination. ----------- This is probably the most requested section of the document for people whom are starting out on the SNES and want to learn just how in the hell the SNES -DOES- do it's graphics. There's so much to explain!!! The SNES does it's graphics in tiles (surprise surprise!). There are different MODEs on the SNES; the most famous being is MODE 7. Alas: Most people think using $2106 is MODE 7 ($2106 is for screen pixelation: Where the pixels get "larger". Look in Section 1 for an explaination of this register). *** THIS IS NOT MODE 7!!! ***. So the next time the pixels get really "big" (almost making them look like IBM PC 320x200x256 mode :-)), and your friend says "WOW! MODE 7 is COOL," punch 'em in the nose for me. Just kidding. Also, another thing I should mention: Bitplanes are NOT THE SAME AS PLANES. Planes are like "screens." You can scroll a plane, but not a bitplane. Bitplanes are put ONTO a plane, which can be scrolled any direction. I'll be explaining MODE 1. MODE 7 is too tough for me to explain, since you end up losing colors and other screwy things... Check Section-5 for a mode-# list. MODE #/Playfields MaxColor/Tile Palettes Colors --------------------------------------------------------------------------- 0 4 4 8 16 1 3 16/16/4 (HUH?) 8 128 MODE 0 is good for geometric shapes (if you were going to rotate a wireframe cube), basic star scrolls, or a very "bland" text scroller. Let's start with MODE 1. MODE 1 is best for really basic things: Star scrollers, text scrolls, geometric (non detailed) art, or line drawings; it's only 16 colors/bitplane, and there's only 4 bitplanes to play with. What you need is 4 bitplanes of data. You don't -HAVE- to use 4 bitplanes... You can use 1 bitplane if you want, but you only get 16 colors (NO!!! :-)). You also need a plane map: You can't just have the predefined graphics data and thats it: You have to "setup the plane" to tell it what tile goes where. For demonstration purposes, i'll use code to explain it. ----------- The "lda #$0000" "tcd" transfers the DP location pointer to where the scratchpad RAM is. This makes things go much faster, because DP is always faster than normal RAM (yay for DP!!!) The other part puts where the location of the data in the binary/image is into two DP locations: font and font2. font equ $00 ; Direct page equates. font2 equ font+1 sei phk plb clc xce rep #$30 lda #$0000 tcd lda #charset sta font lda #charset2 sta font2 ----------- The following code tells the SNES where the actual data is in VRAM memory. lda #$10 ; Plane 0 text @ VRAM $1000. sta $2107 lda #$02 ; Tiles for Plane 0 @ VRAM $2000. sta $210b ----------- The following code actually MOVES the data in the binary/image into the SNES's VRAM. sep #$20 ldx #$2000 ; This puts the data sent thru $2118 and ; $2119 into VRAM $2000. stx $2116 ldy #$0000 - lda (font),y ; Get bitplane 0 data (font) sta $2118 ; ... and store it in bitplane 0. lda (font2),y ; Get bitplane 1 data (font2) sta $2119 ; ... and store it in bitplane 1... stz $2118 ; I don't want to use bitplane 2 and 3, stz $2119 ; so I store zeros here. You could put ; more font data in there if you wanted. iny cpy #$0200 bne - ldx #$1000 ; This puts the data sent thru $2118 and stx $2116 ; $2119 into VRAM $1000. ldx #$0000 - lda TEXT,x ; Get the character from TEXT... and #$3f ; AND #$3F because we only want the first ; 64 characters in the font. sta $2118 ; stz $2119 ; Check near the end of this Section for ; an explaination on what the actual bits ; do instead of just storing 0 there all ; the time. inx cpx #$0400 bne - ----------- Here's the actual data names (charset, charset2, and TEXT). My new source has them in dcb % statements to make the font more readable: The first time I did this, I had to convert the binary stuff I wrote on paper into hex, then put them into decent hex statements in an orderly fashion. charset dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'@' dcb $00,$3c,$66,$7e,$66,$66,$66,$00 ;'A' dcb $00,$7c,$66,$7c,$66,$66,$7c,$00 ;'B' dcb $00,$3c,$66,$60,$60,$66,$3c,$00 ;'C' dcb $00,$78,$6c,$66,$66,$6c,$78,$00 ;'D' dcb $00,$7e,$60,$78,$60,$60,$7e,$00 ;'E' dcb $00,$7e,$60,$78,$60,$60,$60,$00 ;'F' dcb $00,$3c,$66,$60,$6e,$66,$3c,$00 ;'G' dcb $00,$66,$66,$7e,$66,$66,$66,$00 ;'H' dcb $00,$3c,$18,$18,$18,$18,$3c,$00 ;'I' dcb $00,$1e,$0c,$0c,$0c,$6c,$38,$00 ;'J' dcb $00,$6c,$78,$70,$78,$6c,$66,$00 ;'K' dcb $00,$60,$60,$60,$60,$60,$7e,$00 ;'L' dcb $00,$63,$77,$7f,$6b,$63,$63,$00 ;'M' dcb $00,$66,$76,$7e,$7e,$6e,$66,$00 ;'N' dcb $00,$3c,$66,$66,$66,$66,$3c,$00 ;'O' dcb $00,$7c,$66,$66,$7c,$60,$60,$00 ;'P' dcb $00,$3c,$66,$66,$66,$3c,$0e,$00 ;'Q' dcb $00,$7c,$66,$66,$7c,$6c,$66,$00 ;'R' dcb $00,$3e,$60,$3c,$06,$66,$3c,$00 ;'S' dcb $00,$7e,$18,$18,$18,$18,$18,$00 ;'T' dcb $00,$66,$66,$66,$66,$66,$3c,$00 ;'U' dcb $00,$66,$66,$66,$66,$3c,$18,$00 ;'V' dcb $00,$63,$63,$6b,$7f,$77,$63,$00 ;'W' dcb $00,$66,$3c,$18,$3c,$66,$66,$00 ;'X' dcb $00,$66,$66,$3c,$18,$18,$18,$00 ;'Y' dcb $00,$7e,$0c,$18,$30,$60,$7e,$00 ;'Z' dcb $08,$00,$00,$00,$00,$00,$00,$00 ;'[' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'\' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;']' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'^' dcb $00,$08,$00,$00,$00,$00,$00,$00 ;'_' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;' ' dcb $00,$7E,$7E,$3C,$18,$00,$18,$00 ;'!' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'"' dcb $80,$80,$80,$80,$80,$80,$80,$80 ;'#' dcb $FC,$FE,$FF,$F7,$F7,$FF,$FE,$FC ;'$' dcb $3E,$42,$4E,$5C,$5C,$4E,$42,$3E ;'%' dcb $00,$00,$00,$00,$00,$00,$00,$01 ;'&' dcb $00,$00,$00,$07,$00,$00,$00,$00 ;''' dcb $00,$04,$08,$08,$08,$08,$04,$00 ;'(' dcb $00,$20,$10,$10,$10,$10,$20,$00 ;')' dcb $08,$08,$08,$F8,$08,$08,$08,$08 ;'*' dcb $10,$10,$10,$1F,$10,$10,$10,$10 ;'+' dcb $10,$10,$20,$C0,$00,$00,$00,$00 ;',' dcb $00,$00,$00,$FF,$00,$00,$00,$00 ;'-' dcb $00,$00,$00,$00,$00,$18,$18,$00 ;'.' dcb $00,$00,$00,$FF,$80,$80,$80,$80 ;'/' dcb $00,$3c,$66,$6e,$76,$66,$3c,$00 ;'0' dcb $00,$18,$38,$18,$18,$18,$7e,$00 ;'1' dcb $00,$7c,$06,$0c,$30,$60,$7e,$00 ;'2' dcb $00,$7e,$06,$1c,$06,$66,$3c,$00 ;'3' dcb $00,$0e,$1e,$36,$7f,$06,$06,$00 ;'4' dcb $00,$7e,$60,$7c,$06,$66,$3c,$00 ;'5' dcb $00,$3e,$60,$7c,$66,$66,$3c,$00 ;'6' dcb $00,$7e,$06,$0c,$0c,$0c,$0c,$00 ;'7' dcb $00,$3c,$66,$3c,$66,$66,$3c,$00 ;'8' dcb $00,$3c,$66,$3e,$06,$66,$3c,$00 ;'9' dcb $00,$00,$00,$03,$04,$08,$08,$08 ;':' dcb $00,$80,$80,$F0,$80,$80,$00,$00 ;';' dcb $80,$80,$80,$FF,$00,$00,$00,$00 ;'<' dcb $00,$00,$00,$C0,$20,$10,$10,$10 ;'=' dcb $08,$08,$04,$03,$00,$00,$00,$00 ;'>' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'?' charset2 dcb $00,$3C,$4E,$5E,$5E,$40,$3C,$00 ;'@' dcb $00,$3c,$66,$7e,$66,$66,$66,$00 ;'A' dcb $00,$7c,$66,$7c,$66,$66,$7c,$00 ;'B' dcb $00,$3c,$66,$60,$60,$66,$3c,$00 ;'C' dcb $00,$78,$6c,$66,$66,$6c,$78,$00 ;'D' dcb $00,$7e,$60,$78,$60,$60,$7e,$00 ;'E' dcb $00,$7e,$60,$78,$60,$60,$60,$00 ;'F' dcb $00,$3c,$66,$60,$6e,$66,$3c,$00 ;'G' dcb $00,$66,$66,$7e,$66,$66,$66,$00 ;'H' dcb $00,$3c,$18,$18,$18,$18,$3c,$00 ;'I' dcb $00,$1e,$0c,$0c,$0c,$6c,$38,$00 ;'J' dcb $00,$6c,$78,$70,$78,$6c,$66,$00 ;'K' dcb $00,$60,$60,$60,$60,$60,$7e,$00 ;'L' dcb $00,$63,$77,$7f,$6b,$63,$63,$00 ;'M' dcb $00,$66,$76,$7e,$7e,$6e,$66,$00 ;'N' dcb $00,$3c,$66,$66,$66,$66,$3c,$00 ;'O' dcb $00,$7c,$66,$66,$7c,$60,$60,$00 ;'P' dcb $00,$3c,$66,$66,$66,$3c,$0e,$00 ;'Q' dcb $00,$7c,$66,$66,$7c,$6c,$66,$00 ;'R' dcb $00,$3e,$60,$3c,$06,$66,$3c,$00 ;'S' dcb $00,$7e,$18,$18,$18,$18,$18,$00 ;'T' dcb $00,$66,$66,$66,$66,$66,$3c,$00 ;'U' dcb $00,$66,$66,$66,$66,$3c,$18,$00 ;'V' dcb $00,$63,$63,$6b,$7f,$77,$63,$00 ;'W' dcb $00,$66,$3c,$18,$3c,$66,$66,$00 ;'X' dcb $00,$66,$66,$3c,$18,$18,$18,$00 ;'Y' dcb $00,$7e,$0c,$18,$30,$60,$7e,$00 ;'Z' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'[' dcb $09,$09,$00,$00,$00,$00,$00,$00 ;'\' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;']' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'^' dcb $00,$08,$00,$00,$00,$00,$00,$00 ;'_' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;' ' dcb $00,$7E,$7E,$3C,$18,$00,$18,$00 ;'!' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'"' dcb $80,$80,$80,$80,$80,$80,$80,$80 ;'#' dcb $FC,$FE,$FF,$F7,$F7,$FF,$FE,$FC ;'$' dcb $3E,$42,$4E,$5C,$5C,$4E,$42,$3E ;'%' dcb $00,$00,$00,$00,$00,$00,$00,$01 ;'&' dcb $00,$00,$00,$07,$00,$00,$00,$00 ;''' dcb $00,$04,$08,$08,$08,$08,$04,$00 ;'(' dcb $00,$20,$10,$10,$10,$10,$20,$00 ;')' dcb $08,$08,$08,$F8,$08,$08,$08,$08 ;'*' dcb $10,$10,$10,$1F,$10,$10,$10,$10 ;'+' dcb $10,$10,$20,$C0,$00,$00,$00,$00 ;',' dcb $00,$00,$00,$FF,$00,$00,$00,$00 ;'-' dcb $00,$00,$00,$00,$00,$18,$18,$00 ;'.' dcb $00,$00,$00,$FF,$80,$80,$80,$80 ;'/' dcb $00,$3c,$66,$6e,$76,$66,$3c,$00 ;'0' dcb $00,$18,$38,$18,$18,$18,$7e,$00 ;'1' dcb $00,$7c,$06,$0c,$30,$60,$7e,$00 ;'2' dcb $00,$7e,$06,$1c,$06,$66,$3c,$00 ;'3' dcb $00,$0e,$1e,$36,$7f,$06,$06,$00 ;'4' dcb $00,$7e,$60,$7c,$06,$66,$3c,$00 ;'5' dcb $00,$3e,$60,$7c,$66,$66,$3c,$00 ;'6' dcb $00,$7e,$06,$0c,$0c,$0c,$0c,$00 ;'7' dcb $00,$3c,$66,$3c,$66,$66,$3c,$00 ;'8' dcb $00,$3c,$66,$3e,$06,$66,$3c,$00 ;'9' dcb $00,$00,$00,$03,$04,$08,$08,$08 ;':' dcb $00,$80,$80,$F0,$80,$80,$00,$00 ;';' dcb $80,$80,$80,$FF,$00,$00,$00,$00 ;'<' dcb $00,$00,$00,$C0,$20,$10,$10,$10 ;'=' dcb $08,$08,$04,$03,$00,$00,$00,$00 ;'>' dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'?' TEXT dcb " THIS IS YOUR ENTIRE SCREEN " dcb " HERE... IF YOU REMOVE ONE OF " dcb " THE LINES WHICH IS BLANK, THE " dcb " SCREEN ENDS UP BEING FUNKY " dcb " DOWN AT THE BOTTOM OF THE " dcb " SCREEN. " dcb " " dcb " SO MAKE SURE YOU ALWAYS LEAVE " dcb " ALL OF THIS TEXT THINGS IN! " dcb " " dcb " " dcb " " dcb " YOSHI THE DINO " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb " " dcb "********************************" dcb " " dcb " " ----------- Well there's some code for those whom want to rip it :-). I hope I haven't confused you yet: If I have, go back and re-read the code. I've been working with the SNES for awhile, so I under- stand a little more than a beginner. You're probably wondering how the heck the following line ends up being an "@" on your TV, or whatever you have your SNES hooked up to. Lets look at charset and charset2. charset dcb $00,$00,$00,$00,$00,$00,$00,$00 ;'@' charset2 dcb $00,$3C,$4E,$5E,$5E,$40,$3C,$00 ;'@' Convert charsets hex-statements into binary. Consider each new "$xx" statement a new pixel line. Tile size is 8x8. 00000000 = $00 00000000 = $00 00000000 = $00 00000000 = $00 00000000 = $00 00000000 = $00 00000000 = $00 00000000 = $00 Convert charset2s hex-statements into binary. 00000000 = $00 00111100 = $3C 01001110 = $4E 01011110 = $5E 01011110 = $5E 01000000 = $40 00111100 = $3C 00000000 = $00 *NOW* do you see the at-symbol? (and yes, I -DID- draw all of the font by hand. It took me HOURS, but I did it). You're probably now asking: "Well, that tells me how to define where a pixel IS: but how do I define it's color?" This is the fun part. It's sort-of hard to explain: If you have a 0 for bitplane 0, a 0 for bitplane 1, a 0 for bitplane 2, and a 0 for bitplane 3, you get the color 0. i.e.: 0000 = Color #0 ||||___________Bitplane 0 |||__________Bitplane 1 ||_________Bitplane 2 |________Bitplane 3 So, think about a 0 for bitplane 0, a 1 for bitplane 1 & 2 and a 0 for bitplane 3. i.e.: 0110 = Color #6 ||||___________Bitplane 0 |||__________Bitplane 1 ||_________Bitplane 2 |________Bitplane 3 This is probably the best explaination i've ever seen done about SNES pixel-color definition, so don't plan on seeing one any better anytime soon :-). Anyway, the result above gives you the color # per pixel; it's fairly interesting... it's like an "overlay" type of method. I mentioned in the source above that you should check near the end of the Section for info on why I "stz $2119". Well, here's why: The bits in the tile-data are fairly "silly": The tile "character" itself is 10 bits, while the other 6 are "fun bits," as I call them. Here's the explaination: yx?cccNN | NNNNNNNN y: Flip the tile vertically. x: Flip the tile horiztonally. ?: Dunno! Set it to 1 and find out. c: Pallete # (0-7). N: Character itself. So, I STZ there: Yes, I leave the top bits "unset," which means you could get messed up data, but as far as I have checked, the SNES has "clear memory" when you start it up: So the bits I don't zero-out should be zeros anyways! :-) If you want to set them, feel free to do so! The results of flipping Y and X are sortof fun to play with. "To read this scrolly, you must stand on your head" :-) =-=-= 5) SNES Screen mode definitions. ----------- MODE # of bitplanes Colors per plane Palletes Max. # of colors --------------------------------------------------------------------------- 0 2 4 8 32 1 4 16 8 128 2 ? ??? ? ??? 3 8 256 1 256 4 ? ??? ? ??? 5 ? ??? ? ??? 6 ? 16 8 128 (Interlaced mode) 7 ? 256 1 256 (Yes, MODE 7) --------------------------------------------------------------------------- The parms which have "?" or "???" mean I don't know what they REALLY are: I got a document which explained them, but it was bogus: It said a 16 color mode had -1- bitplane. Weird... I'm not even sure about MODE 6. But, we know what MODE 7 is, even if I'm not sure how many bitplanes it DOES use (the doc says 1, I say 8). I've tested MODE 0 and 1 myself. MODE 3 I might test in the future, but i've never had the desire to draw up 8 bitplanes of data by hand ( I don't have a SNES-graphics-generator for the PC! :-( ). =-=-= 6) SNES OAM/Sprite explaination. ----------- The sprites use a lookup table that contains info on their X and Y position on the screen, their size, if they're flipped horizontally or vertically, their color, and the actual character. The format you need to make the table in is as follows: Size Address/Offset Explaination --------------------------------------------------------------------------- *** SPRITE 0 *** BYTE 0 xxxxxxxx x: X location. BYTE 1 yyyyyyyy y: Y location. WORD 2+3 abcdeeex | xxxxxxxx a: Vertical flip. b: Horizontal flip. c: Playfield priority. d: Playfield priority. e: Pallete #. x: Character #. *** SPRITE 0 *** BYTE 4 xxxxxxxx x: X location. BYTE 5 yyyyyyyy y: Y location. ....... and so on ....... --------------------------------------------------------------------------- Continue this table all the way down to sprite #127 (the 128th sprite). Don't think you'redocs/snesmap2.txt0000755000000000000000000012256011266514576011213 0ustar ADDRESS : $2100 NAME : INIDISP CONTENTS : INITIAL SETTINGS FOR SCREEN D7 BLANKING: FORCED BLANKING, 0:NON-BLANKING,1:BLANKING. D6-D4 --- D3-D0 FADE IN/OUT: 0000-DARKEST,1111-BRIGHTEST. ADDRESS : $2101 NAME : OBSEL CONTENTS : OBJECT SIZE & OBJECT DATA AREA DESIGNATION D7-D5 SIZE SELECT: D7 D6 D5 0 1 (SIZE LARGE/SMALL) 0 0 0 8 16 0 0 1 8 32 0 1 0 8 64 0 1 1 16 32 1 0 0 16 64 1 0 1 32 64 (DOTS.) D4-D3 NAME SELECT THE UPPER 4K-WORD OUT OF THE AREA (8K-WORD) DESIGNATED BY "OBJECT BASE ADDRESS" IS ASSIGNED AS THE BASE AREA, AND THE AREA OF THE LOWER 4K- WORD COMBINED WITH ITS BASE AREA CAN BE SELECTED. (SEE APPENDIX 1 & 2) D2-D0 NAME BASE SELECT (UPPER-3 BIT) DESIGNATE THE SEGMENT (8K-WORD) ADDRESS WHICH THE OBJ DATA IS STORED IN VRAM. (APPENDIX 1 & 2) ADDRESS : $2102/$2103 NAME : OAMADDL/OAMADDH CONTENTS : ADDRESS FOR ACCESSING OAM D7-D0 OAM ADDRESS (A7-A0) 2102H D7 OAM PRIORITY ROTATION 2103H D6-D1 --- D0 OAM ADDRESS MSB (A8) THIS IS THE INITIAL ADDRESS TO BE SET IN ADVANCE WHEN READING READING FROM THE OAM OR WRITING TO THE OAM. BY WRITING "1" TO D7 OF REGISTER <2103H> AND SETTING THE OAM- ADDRESS THE OBJ FOR THE ADDRESS SET HAS HIGHEST PRIORITY. THE ADDRESS WHICH HAS BEEN SET JUST BEFORE EVERY FIELD (BEGINNING OF V-BLANK) WILL BE SET AGAIN TO REGISTERS <2102H> <2103H> AUTOMATICALLY. BUT, THE ADDRESS CAN NOT BE SET AUTOMATICALLY DURING FORCED BLANK PERIOD. ADDRESS : $2104 NAME : OAMDATA CONTENTS : DATA FOR OAM WRITE D7-D0 OAM DATA (LOW,HIGH) THIS IS THE OAM DATA TO BE WRITTING AT ANY ADDRESS OF THE OAM. (SEE APPENDIX-3) AFTER REGISTER <2102H> OR <2103H> IS ACCESSED, THE DATA MUST BE WRITTEN IN THE ORDER OF LOWER 8-BIT & UPPER 8-BIT OF REGISTER <2104H>. THE DATA CAN BE WRITTEN ONLY DURING V-BLANK OR FORCED BLANK PERIOD. ADDRESS : $2105 NAME : BGMODE CONTENTS : BG MODE & CHARACTER SIZE SETTINGS D7-D4 BG SIZE DESIGNATION (BG4-BG1) 0: 8 x 8 DOT/CHARACTER 1: 16 x 16 DOT/CHARACTER D3 HIGHEST PRIORITY DESIGNATION FOR BG-3 IN MODE 1 0: OFF (SEE APPENDIX-16) 1: ON D2-D0 BG SCREEN MODE SELECT (SEE APPENDIX-5) ADDRESS : $2106 NAME : MOSAIC CONTENTS : SIZE & SCREEN DESIGNATION FOR MOSAIC DISPLAY D7-D4 MOSAIC SIZE (SEE APPENDIX-6) 1111 - LARGEST, 0000 - SMALLEST. D3-D0 MOSAIC ENABLE (BG4-B1) 0: OFF 1: ON ADDRESS : $2107/$2108/$2109/$210A NAME : BG1SC/BG2SC/BG3SC/BG4SC CONTENTS : ADDRESS FOR STORING SC-DATA OF EACH BG & SC SIZE DESIGNATION D7-D2 SC BASE ADDRESS DESIGNATE THE SEGMENT WHICH BG-SC IN THE VRAM IS STORED. (1K-WORD/SEGMENT) D1-D0 SC SIZE DESIGNATE BACKGROUND SCREEN SIZE (APPENDIX-18 & 19) 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 1 0 1 2 3 ADDRESS : $210B/$210C NAME : BG12NBA/BG34NBA CONTENTS : BG CHARACTER DATA ARE DESIGNATION D7-D4 BG2 BASE ADDRESS 210BH D3-D0 BG1 BASE ADDRESS D7-D4 BG4 BASE ADDRESS 210CH D3-D0 BG3 BASE ADDRESS BACKGROUND NAME BASE ADDRESS (UPPER 4-BIT), SEGMENT ADDRESS IN THE VRAM WHERE BG CHARACTER DATA IS STORED. (4K-WORD/SEGMENT) ADDRESS : $210D/$210E/$210F/$2110/$2111/$2112/$2113/$2114 NAME : BG1HOFS/BG1VOFS/BG2HOFS/BG2VOFS/BG3HOFS/BG3VOFS/BG4HOFS/BG4VOFS CONTENTS : H/V SCROLL VALUE DESIGNATION FOR BG D7-D0 H-OFFSET (LOW,HIGH) HOFS D7-D0 V-OFFSET (LOW,HIGH) VOFS 10 BIT MAXIMUM (0-1023) CAN BE DESIGNATED FOR H/V SCROLL VALUE. [THE SIZE OF 13-BIT MAXIMUM (-4096->4095) CAN BE DESIGNATED IN MODE 7] (SEE APPENDIX-8 & 9) BY WRITING TO THE REGISTER TWICE, THE DATA CAN BE SET IN ORDER OF LOW & HIGH. ADDRESS : $2115 NAME : VMAIN CONTENTS : VRAM ADDRESS INCREMENT VALUE DESIGNATION D7 H/L INC (WORD OR BYTE VRAM ACCESS) DESIGNATE THE INCREMENT TIMING FOR THE ADDRESS 0: THE ADDRESS WILL BE INCREASED AFTER THE DATA HAS BEEN WRITTEN TO REGISTER <2118H> OR THE DATA HAS BEEN READ FROM REGISTER <2139H>. THIS WILL RESULT IN BYTE VRAM ACCESS, I.E. FOR MODE 7 TILE MAP CHANGE. 1: THE ADDRESS WILL BE INCREASED AFTER THE DATA HAS BEEN WRITTEN TO REGISTER <2119H> OR THE DATA HAS BEEN READ FROM REGISTER <213AH>. THIS WILL RESULT IN WORD VRAM ACCESS, I.E. FOR MODE 1 TILE MAP CHANGE. D6-D4 --- D3-D2 FULL GRAPHIC (G1 & G0) D1-D0 SC INCREMENT (I1 & I0) G1 G0 I1 I0 | INCREMENT VALUE ---------------------------- 0 1 0 0 | INCREMENT BY 8 FOR 32 TIMES (2-BIT FORMATION) 1 0 0 0 | INCREMENT BY 8 FOR 64 TIMES (4-BIT FORMATION) 1 1 0 0 | INCREMENT BY 8 FOR 128 TIMES (8-BIT FORMATION) 0 0 0 0 | ADDRESS INCREMENTS 1 BY 1 0 0 0 1 | ADDRESS INCREMENTS 32 BY 32 0 0 1 0 | ADDRESS INCREMENTS 64 BY 64 0 0 1 1 | ADDRESS INCREMENTS 128 BY 128 ADDRESS : $2116/$2117 NAME : VMADDL/VMADDH CONTENTS : ADDRESS FOR VRAM READ D7-D0 VRAM ADDRESS (LOW) 2116H D7-D0 VRAM ADDRESS (HIGH) 2117H THIS IS THE INITIAL ADDRESS FOR READING FROM THE VRAM OR WRITING TO THE VRAM. THE DATA IS READ OR WRITTEN BY THE ADDRESS SET INITIALLY, AND EVERY TIME THE DATA IS READ THE ADDRESS WIL BE INCREASED AUTOMATICALLY. THE VALUE TO BE INCREASED IS DETERMINED BY "SC INCREMENT" OF REGISTER <2115H> AND THE SETTING VALUE OF THE "FULL GRAPHIC". ADDRESS : $2118/$2119 NAME : VMDATAL/VMDATAH CONTENTS : DATA FOR VRAM WRITE D7-D0 VRAM DATA (LOW) 2118H D7-D0 VRAM DATA (HIGH) 2119H THIS IS THE SCREEN DATA AND CHARACTER DATA (BG & OBJ), WHICH CAN WRITE AT ANY ADDRESS OF THE VRAM. ACCORDING TO THE SETTING OF REGISTER <2115H> "H/L INC.", THE DATA CAN BE WRITTEN TO THE VRAM AS FOLLOWS: H/L INC | WRITE TO REGISTER | OPERATION -------------------------------------------------------------- 0 | WRITE TO <2118H> | THE DATA IS WRITTEN TO LOWER 8BIT | ONLY. | OF THE VRAM & THE ADDRESS WILL BE | | INCREASED AUTOMATICALLY. 1 | WRITE TO <2119H> | THE DATA IS WRITTEN TO UPPER 8BIT | ONLY. | OF THE VRAM & THE ADDRESS WILL BE | | INCREASED AUTOMATICALLY. 0 | WRITE IN ORDER OF | WHEN THE DATA IS SET IN THE ORDER | <2119H> & <2118H> | OF UPPER & LOWER THE ADDRESS WILL | | BE INCREASED. 1 | WRITE IN ORDER OF | WHEN THE DATA IS SET IN THE ORDER | <2118H> & <2119H> | OF LOWER & UPPER THE ADDRESS WILL | | BE INCREASED. NOTE: THE DATA CAN ONLY BE WRITTEN DURING V-BLANK OR FORCED BLANK ~~~~~ PERIOD. ADDRESS : $211A NAME : M7SEL CONTENTS : INITIAL SETTING IN SCREEN MODE-7 D7-D6 SCREEN OVER (O1 & O0) PROCESS MADE IF THE SCREEN TO BE DISPLAYED IS OUTSIDE OF THE SCREEN AREA. (SEE BELOW) D5-D2 --- D1-D0 SCREEN FLIP (V/H) 0: NORMAL 1: FLIPPED O1 O0 | PROCESS OUT OF AREA -------------------------------------------------------------- 0 0 | SCREEN REPETITION IF OUTSIDE OF SCREEN AREA 1 0 | CHARACTER 0x00 REPETITION IF OUTSIDE OF SCREEN AREA 1 1 | OUTSIDE OF THE SCREEN AREA IS THE BACK DROP SCREEN IN | SINGLE COLOR ADDRESS : $211B/$211C/$211D/$211E/$211F/$2120 NAME : M7A/M7B/M7C/M7D/M7X/M7Y CONTENTS : ROTATION/ENLARGEMENT/REDUCTION IN MODE-7, CENTER COORDINATE SETTINGS & MULTIPLICAND/MULTIPLIER SETTINGS OF COMPLEMENTARY MULTIPLICATION. D7-D0 MATRIX PARAMETER A (LOW[MP7-MP0],HIGH[MP15-MP8])211BH D7-D0 MATRIX PARAMETER B (LOW[MP7-MP0],HIGH[MP15-MP8])211CH D7-D0 MATRIX PARAMETER C (LOW[MP7-MP0],HIGH[MP15-MP8])211DH D7-D0 MATRIX PARAMETER D (LOW[MP7-MP0],HIGH[MP15-MP8])211EH THE 8-BIT DATA SHOULD BE WRITTEN TWICE IN THE ORDER OF LOWER & UPPER. THEN, THE PARAMETER OF ROTATION, ENLARGEMENT AND REDUCTION SHOULD BE SET BY ITS 16-BIT AREA. THE VALUE DOWN TO A DECIMAL POINT SHOULD BE SET TO THE LOWER 8-BIT. THE MOST SIGNIFICANT BIT OF THE UPPER 8-BIT IS FOR THE SIGNED BIT. (MP15 IS THE SIGNED BIT. THERE IS A DECIMAL POINT BETWEEN M7 & M8) FORMULA FOR ROTAION/ENLARGEMENT/REDUCTION (SEE APPENDIX-13) / X2 \ / A B \ / X1-X0 \ / X0 \ | | = | | | | + | | \ Y2 / \ C D / \ Y1-Y0 / \ Y0 / A=COS(GAMMA)*(1/ALPHA), B=SIN(GAMMA)*(1/ALPHA) C=-SIN(GAMMA)*(1/BETA), D=COS(GAMMA)*(1/BETA) GAMMA: ROTATION ANGLE ALPHA: REDUCTION RATES FOR X(H) BETA : REDUCTION RATES FOR Y(V) X0&Y0: CENTER COORDINATE X1&Y1: DISPLAY COORDINATE X2&Y2: COORDINATE BEFORE CALCULATION SET THE VALUE OF "A" TO REGISTER <211BH>. IN THE SAME WAY, SET "B-D" TO THE REGISTERS <211CH>-<211EH>. * THE COMPLEMENTARY MULTIPLICATION (16BIT X 8BIT) CAN BE DONE BY USING REGISTERS <211BH> <211C>. WHEN SETTING 16 BIT DATA TO REGISTER <211BH> AND 8BIT DATA TO REGISTER <211CH>, THE MULTIPLICATION RESULT CAN BE INDICATED RAPIDLY BY READING REGISTERS <2134H>-<2136H>. D7-D0 CENTER POSITION X0 (LOW[X7-X0],HIGH[X12-X8]) 211FH D7-D0 CENTER POSITION Y0 (LOW[Y7-X0],HIGH[Y12-X8]) 2120H THE CENTER COORDINATE (X0,Y0) FOR ROTATION/ENLARGEMENT/REDUCTION CAN BE DESIGNATED BY THIS REGISTER. THE COORDINATE VALUE OF X0 & Y0 CAN BE DESIGNATED BY 13-BIT (COMPLEMENT OF 2). THE REGISTER REQUIRES THAT THE LOWER 8-BIT IS SET FIRST AND THE UPPER 5-BIT IS SET. THEREFORE, 13-BIT DATA IN TOTAL CAN BE SET. ADDRESS : $2121 NAME : CGADD CONTENTS : ADDRESS FOR CG-RAM WRITE D7-D0 CG-RAM ADDRESS THIS IS THE INITIAL ADDRESS FOR READING FROM THE CG-RAM OR WRITING TO THE CG-RAM THE DATA IS READ BY THE ADDRESS SET INITIALLY, AND EVERY TIME THE DATA IS READ OR WRITTEN THE ADDRESS WILL BE INCREASED AUTOMATICALLY. ADDRESS : $2122 NAME : CGDATA CONTENTS : DATA FOR CG-RAM WRITE D7-D0 CG-RAM DATA (LOW[D7-D0],HIGH[D14-D8]) THIS IS THE COLOR GENERATER DATA TO BE WRITTEN AT ANY ADDRESS OF THE CG-RAM. THE MAPPING OF BG1-BG4 AND OBJ DATA IN CG-RAM WILL BE DETERMINED, WHICH IS PERFORMED BY EVERY MODE SELECTED BY "BG MODE" OF REGISTER <2105H>. (SEE APPENDIX-14) THERE AREA THE COLOR DATA OF 8-PALETTES FOR EACH SCREEN OF BG1-BG4. THE PALETTE SELECTION IS DETERMINED BY 3-BIT OF THE SC DATA "COLOR" BECAUSE THE CG-RAM DATA IS 15-BIT/WORD, IT IS NECESSARY TO SET LOWER 8-BIT FIRST TO THIS REGISTER AND THE THE UPPER 7-BIT. WHEN BOTH LOWER & UPPER ARE SET, THE ADDRESS WILL BE INCREASED BY 1 AUTOMATICALLY. NOTE: AFTER THE ADDRESS IS SET, THE DATA SHOULD BE WRITTEN FROM ~~~~~ THE LOWER AS WELL AS THE OAM. NOTE: THE DATA CAN BE WRITTEN ONLY DURING H/V BLANK OR FORCED- ~~~~~ BLANK PERIOD. ADDRESS : $2123/$2124/$2125 NAME : W12SEL/W34SEL/WOBJSEL CONTENTS : WINDOW MASK SETTINS (BG1-BG4, OBJ, COLOR) D7 BG2 WINDOW-2 ENABLE 2123H 0: OFF 1: ON D6 BG2 WINDOW-2 IN/OUT THE WINDOW MASK AREA CAN BE DESIGNATED WHETHER INSIDE OR OUTSIDE OF THE FRAME DESIGNATED BY THE WINDOW POSITION. 0: IN 1: OUT D5 BG2 WINDOW-1 ENABLE D4 BG2 WINDOW-1 IN/OUT D3 BG1 WINDOW-2 ENABLE D2 BG1 WINDOW-2 IN/OUT D1 BG1 WINDOW-1 ENABLE D0 BG1 WINDOW-1 IN/OUT D7 COLOR WINDOW-2 ENABLE 2125H D6 COLOR WINDOW-2 IN/OUT D5 COLOR WINDOW-1 ENABLE D4 COLOR WINDOW-1 IN/OUT D3 OBJ WINDOW-2 ENABLE D2 OBJ WINDOW-2 IN/OUT D1 OBJ WINDOW-1 ENABLE D0 OBJ WINDOW-1 IN/OUT THE COLOR WINDOW IS A WINDOW FOR MAIN & SUB SCREEN (IT IS RELATED TO REGISTER <2130H>. ADDRESS : $2126/$2127/$2128/$2129 NAME : WH0/WH1/WH2/WH3 CONTENTS : WINDOW POSITION DESIGNATION (SEE APPENDIX-15) D7-D0 WINDOW PPOSITION H0,H2 LEFT POSITION DESIGNATION H1,H3 RIGHT POSITION DESIGNATION NOTE: IF "LEFT POSITION SETTING VALUE > RIGHT POSITION VALUE" ~~~~~ IS ASSUMED, THERE WILL BE NO RANGE OF THE WINDOW. ADDRESS : $212A/$212B NAME : WBGLOG/WOBJLOG CONTENTS : MASK LOGIC SETTINGS FOR WINDOW-1 & 2 ON EACH SCREEN D7-D6 BG4 D1/D0 212AH D5-D4 BG3 D1/D0 D3-D2 BG2 D1/D0 D1-D0 BG1 D1/D0 D7-D4 --- 212BH D3-D2 COLORWINDOW D1/D0 D1-D0 OBJWINDOW D1/D0 D1 D0 | LOGIC ------------------ 0 0 | OR 0 1 | AND 1 0 | XOR 1 1 | XNOR NOTE: "IN/OUT" OF REGISTERS <2123H>-<2125H> BECOMES THE ~~~~~ "NOT-LOGIC" FOR EACH WINDOW-1 & WINDOW-2. ADDRESS : $212C NAME : TM CONTENTS : MAIN SCREEN, DESIGNATION D7-D5 --- D4 OBJ D3 BG4 D2 BG3 D1 BG2 D0 BG1 MAIN SCREEN DESIGNATION: DESIGNATE THE SCREEN (BG1-BG4, OBJ) TO BE DISPLAYED AS THE MAIN SCREEN. DESIGNATE THE SCREEN TO BE ADDED FOR THE SCREEN ADDITION/SUBTRACTION 0: DISABLE 1: ENABLE ADDRESS : $212D NAME : TS CONTENTS : SUB SCREEN DESIGNATION D7-D5 --- D4 OBJ D3 BG4 D2 BG3 D1 BG2 D0 BG1 SUB SCREEN DESIGNATION: DESIGNATE THE SCREEN (BG1-BG4, OBJ) TO BE DISPLAYED AS SUB SCREEN. DESIGNATE THE ADDITION/SUBTRACTION SCREEN AT THE POINT WHEN THE SCREEN ADDITION/SUBTRACTION IS FUNCTIONING. 0: DISABLE 1: ENABLE * WHEN THE SCREEN ADDITION/SUBTRACTION IS FUNCTIONING, THE SUB SCREEN IS A SCREEN TO BE ADDED OR SUBTRACTED AGAINST THE MAIN SCREEN. ADDRESS : $212E NAME : TMW CONTENTS : WINDOW MASK DESIGNATION FOR MAIN SCREEN D7-D5 --- D4 OBJ D3 BG4 D2 BG3 D1 BG2 D0 BG1 WINDOW MASK DESIGNATION FOR MAIN SCREEN: IN THE WINDOW AREA DESIGNATED BY REGISTER <2123H>-<2129H>, THE SCREEN TO BE DISPLAYED CAN BE DESIGNATED, WHICH IS SELECTED AMONG THE MAIN SCREEN DESIGNATED BY REGISTER <212CH>. 0: DISABLE 1: ENABLE ADDRESS : $212F NAME : TSW CONTENTS : WINDOW MASK DESIGNATION FOR SUB SCREEN D7-D5 --- D4 OBJ D3 BG4 D2 BG3 D1 BG2 D0 BG1 WINDOW MASK DESIGNATION FOR SUB SCREEN: IN THE WINDOW AREA DESIGNATED BY REGISTER <2123H>-<2129H>, THE SCREEN TO BE DISPLAYED CAN BE DESIGNATED, WHICH IS SELECTED AMONG THE SUB SCREEN DESIGNATED BY REGISTER <212CH>. 0: DISABLE 1: ENABLE * WHEN THE SCREEN ADDITION/SUBTRACTION IS FUNCTIONING, THE SUB SCREEN IS A SCREEN TO BE ADDED OR SUBTRACTED AGAINST THE MAIN SCREEN. ADDRESS : $2130 NAME : CGWSEL CONTENTS : INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION D7-D6 MAIN SW (M1/M0) D5-D4 SUB SW (S1/S0) D3-D2 --- D1 CC ADD ENABLE, FIXED COLOR ADDITION/SUBTRACTION ENABLE DESIGNATE WHETHER 2 KINDS OF THE DATA SHOULD BE ADDED/SUBTRACTED EACH OTHER OR NOT, WHICH ARE THE FIXED COLOR SET BY REGISTER <2132H>, AND THE COLOR DATA WHICH IS SET TO CGRAM. 0: ADDITION/SUBTRACTION FOR FIXED COLOR 1: ADDITION/SUBTRACTION FOR SUB SCREEN D0 DIRECT SELECT (SEE APPENDIX-14) THE VRAM DATA (COLOR & CHARACTER DATA) BECOME THE COLOR DATA DIRECTLY. [ONLY WHEN MODE-3,4 & 7] 0: DISABLE 1: ENABLE M1(S1) M0(S0) | NORMAL DISPLAY IS: -------------------------------------------------------------- 0 0 | ALL THE TIME 0 1 | INSIDE WINDOW ONLY 1 0 | OUTSIDE WINDOW ONLY 1 1 | ALL THE TIME ADDRESS : $2131 NAME : CGADSUB CONTENTS : ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN, OBJ & BACKGROUND COLOR D7 COLOR DATA ADDITION/SUBTRACTION SELECT DESIGNATE THE SELECTION EITHER OF THE ADDITION OR THE SUBTRACTION MODE. 0: ADDITION MODE SELECT 1: SUBTRACTION MODE SELECT D6 "1/2 OF COLOR DATA" DESIGNATION WHEN THE COLOR CONSTANT ADDITION/SUBTRACTION OR THE SCREEN ADDITION/SUBTRACTION IS PERFORMED, DESIGNATE WHETHER THE RGB RESULT IN THE ADDITION/SUBTRACTION AREA SHOULD BE "1/2" OR NOT. HOWEVER, IN THE BACK COLOR CONSTANT AREA ON THE SUB SCREEN, IT DOES NOT BECOME "1/2" 0: DISABLE 1: ENABLE D5 BACK D4 OBJ D3 BG4 D2 BG3 D1 BG2 D0 BG1 COLOR DATA ADDITION/SUBTRACTION ENABLE 0: DISABLE 1: ENABLE ADDRESS : $2132 NAME : COLDATA CONTENTS : FIXED COLOR DATA FOR FIXED COLOR ADDITION/SUBTRACTION D7 BLUE D6 GREEN D5 RED BIT FOR SELECTING DESIRED COLOR D4-D0 COLOR BRILLIANCE DATA SET THE COLOR CONSTANT DATA FOR COLOR CONSTANT ADDITION/SUBTRACTION * R/G/B BRIGHTNESS SHOULD BE SET BY THE DATA OF EACH 5-BIT. [EXAMPLE] RED : C0H, 3FH (B=00H, G=00H, R=1FH) GREEN : A0H, 5FH (B=00H, G=1FH, R=00H) BLUE : 60H, 9FH (B=1FH, G=00H, R=00H) WHITE : FFH BLACK : 00H ADDRESS : $2133 NAME : SETINI CONTENTS : SCREEN INITIAL SETTING D7 EXTERNAL SYNCHRONIZATION IT IS USED FOR SUPER IMPOSE AND ETC. NORMALLY, "0" SHOULD BE WRITTEN. D6 EXTBG MODE (SCREEN EXPAND) ENABLE THE DATA SUPPLIED FROM THE EXTERNAL LSI. FOR THE SFX, ENABLE WHEN THE SCREEN WITH PRIORITY IS USED ON MODE-7. D5-D4 --- D3 HORIZONTAL PSEUDO 512 MODE 512 IMAGINARY RESOLUTION (HORIZONTAL CAN BE MADE BY SHIFTING THE SUBSCREEN HALF DOT TO THE LEFT.) 0: DISABLE 1: ENABLE D2 BG V-DIRECTION DISPLAY SWITCH THE DISPLAY LINE OF A FIELD TO 224 LINE OR 239 LINE. (IN CASE OF INTERALACE IT WILL BE DOUBLED DOT.) 0: 224 LINE 1: 239 LINE D1 OBJ V-DIRECTION DISPLAY IN THE INTERLACE MODE, SELECT EITHER OF 1-DOT PER LINE OR 1-DOT REPEATED EVERY 2-LINES. IF "1" IS WRITTEN, THE OBJ SEEMS REDUCED HALF VERTICALLY IN APPEARANCE. D0 SCANNING INTERLACE/NON-INTERLACE SELECTION (IT RELATES TO <2105H>. 0: NON INTERLACE 1: INTERLACE ADDRESS : $2134/$2135/$2136 NAME : *MPYL/*MPYM/*MPYH CONTENTS : MULTIPLICATION RESULT D7-D0 MPY (LOW) 2134H D7-D0 MPY (MID) 2135H D7-D0 MPY (HIGH) 2136H THIS IS A MULTIPLICATION RESULT (COMPLEMENT OF 2) CAN BE READ BY SETTING 16-BIT TO REGISTER <211BH> AND SETTING 8 BIT TO REGISTER <211CH> ADDRESS : $2137 NAME : *SLHV CONTENTS : SOFTWARE LATCH FOR H/V COUNTER D7-D0 SOFT LATCH FOR H/V COUNTER THIS IS A REGISTER, WHICH GENERATE THE PULSE FOR LATCHING THE H/V COUNTER VALUE. THE H/V COUNTER VALUE AT THE POINT WHEN REGISTER <2137H> IS READ CAN BE LATCHED. THE DATA WHICH WAS READ IS MEANINGLESS DATA. THE H/V COUNTER VALUE LATCHED CAN BE REFFERED BY REGISTERS <213CH> & <213DH>. ADDRESS : $2138 NAME : OAMDATAREAD (name differs from SNES manual) CONTENTS : READ DATA FROM OAM D7-D0 OAM DATA (LOW,HIGH) THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF THE OAM. WHEN THE ADDRESS IS SET TO REGISTER <2102H><2103H> AND REGISTER <2138H> IS ALSO ACCESSED THE DATA CAN BE READ IN THE ORDER OF LOW 8-BIT/HIGH 8-BIT. AFTERWARD, THE ADDRESS WILL BE INCREASED AUTOMATICALLY, AND THE DATA OF THE NEXT ADDRESS CAN BE READ. NOTE: THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED ~~~~~ BLANK PERIOD. ADDRESS : $2139/$213A NAME : VMDATALREAD/VMDATAHREAD (names differ from SNES manual) CONTENTS : READ DATA FROM VRAM D7-D0 VRAM DATA (LOW) 2139H D7-D0 VRAM DATA (HIGH) 213AH THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF THE VRAM. THE INITIAL ADDRESS SHOULD BE SET BY REGISTERS <2116H> AND <2117H>. THE DATA CAN BE READ BY THE ADDRESS WHICH HAS BEEN SET INITIALLY. WHEN READING THE DATA CONTINOUSLY, THE FIRST DATA FOR THE ADDRESS INCREMENT SHOULD BE READ AS A DUMMY DATA AFTER THE ADDRESS HAS BEEN SET. QUANTITY TO BE INCREASED WILL BE DETERMINED BY "SC INCREMENT" OF REGISTER <2115H> AND THE SETTING VALUE OF THE "FULL GRAPHIC". NOTE: THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED ~~~~~ BLANK PERIOD. ADDRESS : $213B NAME : CGDATAREAD (name differs from SNES manual) CONTENTS : READ DATA FROM CG-RAM D7-D0 CG DATA (LOW,HIGH) THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF THE CG-RAM. THE INITIAL ADDRESS SHOULD BE SET BY REGISTER <2121H>. THE LOWER 8-BIT IS READ FIRST, AND THE THE UPPER 7-BIT WILL BE READ BY ACCESSING THIS REGISTER. THE CURRENT ADDRESS WILL BE INCREASED TO THE NEXT ADDRESS AT THE SAME TIME THE UPPER 7-BIT IS READ. NOTE: THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED ~~~~~ BLANK PERIOD. ADDRESS : $213C/$213D NAME : *OPHCT/*OPVCT CONTENTS : H/V COUNTER DATA BY EXTERNAL OR SOFTWARE LATCH D7-D0 OUTPUT DATA OF H-COUNTER [9-BIT] 213CH D7-D0 OUTPUT DATA OF V-COUNTER [9-BIT] 213DH THE H/V COUNTER IS LATCHED BY READING REGISTER <2137H>, AND ITS H/V COUNTER VALUE CAN BE READ BY THIS REGISTER. THE H/V COUNTER IS ALSO LATCHED BY THE EXTERNAL LATCH, AND ITS VALUE CAN BE READ BY THIS REGISTER. IF REGISTER <213CH> OR <213DH> IS READ AFTER REGISTER <213FH> HAS BEEN READ, THE LOWER 8-BIT DATA WILL BE READ FIRST, AND THEN THE UPPER 1-BIT WILL BE READ BY READING THE REGISTER. ADDRESS : $213E NAME : *STAT77 CONTENTS : PPU STATUS FLAG & VERSION NUMBER D7 TIME OVER \ D6 RANGE OVER / OBJ DISPLAY STATUS (ON A HORIZONTAL LINE) RANGE: WHEN QUANTITY OF THE OBJ (REGARDLESS OF THE SIZE) BECOMES 33 PCS OR MORE, "1" WILL BE SET. TIME: WHEN QUANTITY OF THE OBJ WHICH IS CONVERTED TO "8 x 8-SIZE" IS 35 PCS OR MORE, "1" WILL BE SET. D5 MASTER/SLAVE MODE SELECT. LSI MODE (NORMALLY "0" IS SET.) D4 --- D3-D0 5C77 VERSION NUMBER NOTE: THE FLAG WILL BE RESET AT THE END OF THE V-BLANK PERIOD. ~~~~~ ADDRESS : $213F NAME : *STAT78 CONTENTS : PPU STATUS FLAG & VERSION NUMBER D7 FIELD THIS IS A STATUS FLAG, WHICH INDICATED WHETHER 1ST FIELD IS SCANNED OR 2ND FIELD IS SCANNED IN INTER- LACE MODE. (THE DEFINITION IS DIFFERENT FROM THE FIELD OF NTSC.) 0: 1ST FIELD 1: 2ND FIELD D6 EXTERNAL LATCH FLAG WHEN THE EXTERNAL SIGNAL (LIGHT PEN, ETC.) IS APPLIED, IT ENABLES TO LATCH THE H/V COUNTER VALUE. D5 --- D4 NTSC/PAL MODE 0: NTSC 1: PAL D3-D0 5C78 VERSION NUMBER NOTE: WHEN THIS REGISTER IS READ, REGISTERS <213CH><213DH> WILL ~~~~~ BE INITIALIZED INDIVIDUALLY IN THE ORDER OF LOW & HIGH. ADDRESS : $2140/$2141/$2142/$2143 NAME : APUI00/APUI01/APUI02/APUI03 CONTENTS : COMMUNICATION PORT WITH APU D7-D0 APU I/O PORT THIS PORT PROVIDES MORE REGISTERS FOR THE PURPOSE OF IN/OUT, WHICH ARE 8 REGISTERS IN TOTAL IN THE APU. THEREFORE, THE DIFFERENT REGISTER WILL BE ACCESSED, WHETHER READING OR WRITING FOR THE SAME ADDRESS. SEE "APU MANUAL" FOR THE DETAILS OF THE COMMUNICATION METHOD. ADDRESS : $2180 NAME : WMDATA CONTENTS : DATA TO CONSECUTIVLEY READ FROM AND WRITE TO WRAM D7-D0 WORK RAM DATA DATA TO CONSECUTIVLEY READ FROM AND WRITE TO WRAM DATA IS READ AND WRITTEN AT ADDRESS SET BY REGISTER <2181H>-<2183H>, AND ADDRESS AUTOMATICALLY INCREASES EACH TIME DATA IS READ OR WRITTEN. ADDRESS : $2181/$2182/$2183 NAME : WMADDL/WMADDM/WMADDH CONTENTS : ADDRESS TO CONSECUTIVELY READ AND WRITE WRAM D7-D0 WRAM DATA (LOW) 2181H D7-D0 WRAM DATA (MID) 2182H D0 WRAM DATA (HIGH) 2183H ADDRESS TO BE SET BEFORE WRAM IS CONSECUTIVLEY READ OR WRITTEN. A0 TROUGH A16 AT REGISTER <2181H>-<2183H> IS LOWER 17 BIT ADDRESS TO SHOW ADDRESS $7E0000-$7FFFFF IN MEMORY. ADDRESS : $4200 NAME : NMITIMEN CONTENTS : ENABLE FLAG FOR V-BLANK, TIMER INTERRUPT & JOY CONTROLLER READ D7 NMI ENABLE ENABLE NMI AT THE POINT WHEN V-BLANK BEGINS (WHEN POWER IS TURNED ON OR THE RESET SIGNAL IS APPLIED, IT WILL BE "0".) 0: NMI DISABLED 1: NMI ENABLED D6 --- D5-D4 TIMER ENABLE (V-EN/H-EN) D3-D1 --- D0 JOY-C ENABLE 0: DISABLE AUTOMATIC READING OF THE JOY-CONTROLLER. 1: ENABLE AUTOMATIC READING OF THE JOY-CONTROLLER. V-EN H-EN | FUNCTION -------------------------------------------------------- 0 0 | DISABLE BOTH H & V 0 1 | ENABLE H ONLY, IRQ APPLIED BY H-COUNT TIMER VALUE DESIGNATED 1 0 | ENABLE V ONLY, IRQ APPLIED BY V-COUNT TIMER VALUE DESIGNATED 1 1 | ENABLE BOTH V & H, IRQ APPLIED BY BOTH H & V COUNT TIMER VAL | DESIGNATED. * READING THE DATA CAN BE STARTED AT THE BEGINNING OF V-BLANK PERIOD, BUT IT TAKES ABOUT FOR 3 OR 4 SCANNING PERIOD UNTIL COMPLETION OF READING. ADDRESS : $4201 NAME : WRIO CONTENTS : PROGRAMMABLE I/O PORT (OUT-PORT) D7-D0 I/O PORT THIS IS A PROGRAMMABLE I/O PORT (OUT-PORT). THE WRITTEN DATA WILL BE OUTPUT DIRECTLY FROM THE OUT-PORT. WHEN THIS IS USED AS A INPORT. "1" SHOULD BE WRITTEN TO THE PARTICULAR BIT WHICH WILL BE USED AS IN PORT. THE INPUT CAN BE READ BY REGISTER <4213H>. ADDRESS : $4202/$4203 NAME : WRMPYA/WRMPYB CONTENTS : MULTIPLIER & MULTIPLICAND BY MULTIPLICATION D7-D0 MULTIPLICAND-A 4202H D7-D0 MULTIPLIER-B 4203H THIS IS A REGISTER, WHICH CAN SET A MULITPLICAND (A) AND A MULTIPLIER (B) FOR ABSOLUTE MULTIPLICATION OF "A (8-BIT) * B (8-BIT)=C (16-BIT)" A PRODUCT (C) CAN BE READ BY REGISTERS <4216H><4217H> SET IN THE ORDER OF (A) AND (B). THE OPERATION WILL START AS SOON AS (B) HAS BEEN SET, AND IT WILL BE COMPLETED RIGHT AFTER 8-MACHINE CYCLE PERIOD. ONCE THE DATA OF THE A-REGISTER IS SET, IT WILL NOT BE DESTROYED UNTIL NEW DATA IS SET. ADDRESS : $4204/$4205/$4206 NAME : WRDIVL/WRDIVH/WRDIVB CONTENTS : DIVISOR & DIVIDEND DIVIDE D7-D0 MULTIPLIER-C (LOW) 4204H D7-D0 MULTIPLIER-C (HIGH) 4205H D7-D0 DIVISOR-B 4206H THIS IS A REGISTER, WHICH CAN SET A DIVIDEND (C) AND A DIVISOR (B) FOR ABSOLUTE DIVIDE OF "C (16-BIT) / B (8-BIT)=A (16-BIT)" THE DIVISOR (A) CAN BE READ BY REGISTERS <4214H><4215H>, AND THE REMAINDER CAN ALSO BE READ BY REGISTERS <4216H><4217H>. SET IN THE ORDER OF (C) AND (B). THE OPERATION WILL START AS SOON AS (B) HAS BEEN SET, AND IT WILL BE COMPLETED RIGHT AFTER 16- MACHINE CYCLE PERIOD. ONCE THE DATA OF THE A-REGISTER IS SET, IT WILL NOT BE DESTROYED UNTIL NEW DATA IS SET. ADDRESS : $4207/$4208 NAME : HTIMEL/HTIMEH CONTENTS : H-COUNT TIMER SETTINGS D7-D0 H COUNT TIMER (H7-H0) 4207H D7-D1 --- D0 H COUNT TIMER (H8) 4208H THIS IS A REGISTER, WHICH CAN SET THE H-COUNT TIMER VALUE. THE SETTING VALUE SHOULD BE FROM 0 THROUGH 339, WHICH IS COUNTED FROM THE FAR LEFT ON THE SCREEN. HWEN THE COORDINATE COUNTER BECOMES THE COUNT VALUE SET, THE IRQ WILL BE APPLIED. AND AT THE SAME TIME. "1" WILL BE WRITTEN TO "TIMER IRQ" OF REGISTER <4211H>. (READ RESET) ENABLE/DISABLE OF THE INTERRUPT WILL BE DETERMINED BY SETTING REGISTER <4200H> * THIS CONTINOUS COUNTER IS RESET EVERY SCANNING LINE, THEREFORE ONCE THE COUNT VALUE IS SET, IT IS POSSIBLE TO APPLY THE IRQ EVERY TIME THE SCANNING LINE COMES TO THE SAME HORIZONTAL POSITION ON THE SCREEN. ADDRESS : $4209/$420AH NAME : VTIMEL/VTIMEH CONTENTS : V-COUNT TIMER SETTINGS D7-D0 V COUNT TIMER (V7-V0) 4209H D7-D1 --- D0 V COUNT TIMER (V8) 420AH THIS IS A REGISTER, WHICH CAN SET THE V-COUNT TIMER VALUE. THE SETTING VALUE SHOULD BE FROM 0 THROUGH 261(262), WHICH IS COUNTED FROM THE FAR TOP OF THE SCREEN. [THE LINE NUMBER DESCRIBED IS DIFFERENT FROM THE ACTUAL LINE NUMBER ON THE SCREEN.] HWEN THE COORDINATE COUNTER BECOMES THE COUNT VALUE SET, THE IRQ WILL BE APPLIED. AND AT THE SAME TIME. "1" WILL BE WRITTEN TO "TIMER IRQ" OF REGISTER <4211H>. (READ RESET) ENABLE/DISABLE OF THE INTERRUPT WILL BE DETERMINED BY SETTING REGISTER <4200H> * THIS IS A CONTINOUS COUNTER SAME AS H-COUNTER, AND IT WILL BE RESET EVERY TIME 262(263) LINE ARE SCANNED. ONCE THE COUNT VALUE IS SET, IT IS POSSIBLE TO APPLY THE IRQ EVERY TIME THE SCANNING LINE COMES TO THE SAME VERTICAL LINE ON THE SCREEN. ADDRESS : $420B NAME : MDMAEN CONTENTS : CHANNEL DESIGNATION FOR GENERAL PURPOSE DMA & TRIGGER (START) D7-D0 GENERAL PURPOSE CH7-CH0 ENABLE THE GENERAL PURPOSE DMA CONSISTS OF 8-CHANNELS IN TOTAL. THIS REGISTER IS USED TO DESIGNATE THE CHANNEL OUT OF 8-CHANNELS. THE CHANNEL WHICH SHOULD BE USED CAN BE DESIGNATED BY WRITING "1" TO THE BIT OF THIS CHANNEL. AS SOON AS "1" IS WRITTEN TO THE BIT (AFTER A FEW CYCLES PASSED), THE GENERAL PURPOSE DMA TRANSFER WILL BE STARTED. WHEN THE GENERAL PURPOSE DMA OF THE DESIGNATED CHANNEL IS COMPLETED, THE FLAG WILL BE CLEARED. NOTE: BECAUSE THE DATA AREA (REGISTER <4300>-) OF EACH CHANNEL ~~~~~ IS HELD IN COMMON WITH THE DATA OF EACH H-DMA CHANNEL, THE CHANNEL DESIGNATED BY THE H-DMA CHANNEL DESIGNATION REGISTER <420CH> CAN NOT BE USED. (IT IS PROHIBITED TO WRITE "1" TO THE BIT OF THE CHANNEL) THEREFORE, 8 CHANNELS (CH0-CH7) SHOULD BE ASSIGNED BY THE H-DMA AND THE GENERAL PURPOSE DMA) NOTE: IF THE H-BLANK COME DURING THE OPERATION OF THE GENERAL ~~~~~ PURPOSE DMA AND THE H-DMA IS STARTED, THE GENERAL PURPOSE DMA WILL BE DISCONTINUED IN THE MIDDLE, AND RE-STARTED RIGHT AFTER THE H-DMA IS COMPLETE. NOTE: IF 2 OR MORE CHANNELS ARE DESIGNATED, THE DMA TRANSFER WILL ~~~~~ BE PERFORMED CONTINOUSLY ACCORDING TO THE PRIORITY DESCRIBED IN APPENDIX-1. AND ALSO, THE CPU STOPS OPERATION UNTIL ALL THE GENERAL PURPOSE DMA ARE COMPLETED. ADDRESS : $420C NAME : HDMAEN CONTENTS : CHANNEL DESIGNATION FOR H-DMA D7-D0 H-DMA CH7-DH0 ENABLE THE H-DMA CONSISTS OF 8-CHANNELS IN TOTAL THIS REGISTER IS USED TO DESIGNATE THE CHANNEL OUT OF 8-CHANNELS THE CHANNEL WHICH SHOULD BE USED CAN BE DESIGNATED BY WRITING "1" TO THE BIT OF THIS CHANNEL. AS SOON AS H-BLANK BEGINS (AFTER A FEW CYCLES PASSED), THE H-DMA TRANSFER WILL BE STARTED. NOTE: ONCE THIS FLAG IS SET, IT WILL NOT BE DESTROYED (CLEARED) ~~~~~ UNTIL NEW DATA IS SET. THEREFORE, THE INITIAL SETTINGS ARE DONE AUTOMATICALLY EVERY FIELD, AND THE SAME TRANSFER PATTERN WILL BE REPEATED. AND ALSO, THE FLAG IS SET OUT OF V-BLANK PERIOD, THE DMA- TRANSFER WILL BE PERFORMED PROPERLY FROM NEXT SCREEN FRAME. ADDRESS : $420D NAME : MEMSEL CONTENTS : ACCESS CYCLE DESIGNATION IN MEMORY (2) AREA D7-D1 --- D0 ACCESS CYCLE DESIGNATION IN MEMORY (2) AREA 0: 2.68MHz ACCESS CYCLE 1: 3.58MHz ACCESS CYCLE (ONLY WHEN HIGH SPEED MEMORY IS USED.) MEMORY (2) SHOWS THE ADDRESS (8000H-FFFFH) OF THE BANK (80H-BFH) AND ALL THE ADDRESS OF THE BANK (C0H-FFH). WHEN POWER IS TURNED ON OR THE RESET SIGNAL IS APPLIED IT BECOMES "0". HIGH SPEED MEMORY REQUIERS 120NS OR FASTER EPROMS. ADDRESS : $4210 NAME : *RDNMI CONTENTS : NMI FLAG BY V-BLANK & VERSION NUMBER D7 NMI FLAG BY V-BLANK WHEN "1" IS WRITTEN TO "NMI ENABLE" OF REGISTER <4200H>, THIS FLAG WILL SHOW NMI STATUS. 0: NMI STATUS IS "DISABLE" 1: NMI STATUS IS "ENABLE" D6-D4 --- D3-D0 5A22 VERSION NUMBER * "1" IS SET TO THIS FLAG AT BEGINNING OF V-BLANK, AND "0" IS SET AT END OF V-BLANK. ALSO, IT CAN BE SET BY READING THIS REGISTER. NOTE: IT IS NECESSARY TO RESET BY READING THIS FLAG DURING ~~~~~ NMI PROCESSING. (SEE APPENDIX-3) ADDRESS : $4211 NAME : *TIMEUP CONTENTS : IRQ FLAG BY H/V COUNT TIMER D7 IRQ FLAG BY H/V COUNT TIMER [IN CASE THE TIME ENABLE IS SET BY "TIMER ENABLE" OF REGISTER <4200H>] AS SOON AS H/V COUNTER TIMER BECOMES THE COUNT VALUE SET, IRQ WILL BE APPLIED AND "1" WILL BE SET TO THIS FLAG. THIS FLAG IS "READ-RESET". D6-D0 --- * EVEN IF V-EN="0" AND H-EN="0" ARE SET BY "TIMER ENABLE" OF REGISTER <4200H>, THIS FLAG WILL BE RESET. 0: EITHER H/V COUNTER IS IN ACTIVE OR DISABLE. 1: H/V COUNT TIMER IS TIME UP. ADDRESS : $4212 NAME : HVBJOY CONTENTS : H/V BLANK FLAG & JOY CONTROLLER ENABLE FLAG D7 V-BLANK PERIOD FLAG 0: OUT OF V-BLANK PERIOD 1: IN V-BLANK PERIOD D6 H-BLANK PERIOD FLAG 0: OUT OF H-BLANK PERIOD 1: IN H-BLANK PERIOD D5-D1 --- D0 JOY CONTROLLER ENABLE FLAG THIS FLAG SHOWS THE TIMING TO READ THE DATA OF THE JOY CONTROLLER. (HOWEVER, IT IS LIMITED TO THE CASE WHICH THE "JOY-C ENABLE" OF REGISTER <4200H> IS SET TO "1". ADDRESS : $4213 NAME : *RDIO CONTENTS : PROGRAMMABLE I/O PORT (IN-PORT) D7-D0 I/O PORT THIS IS A PROGRAMMABLE I/O PORT (IN PORT). THE DATA WHICH IS SET TO THE IN-PORT SHOULD BE READ DIRECTLY. THE BIT WHICH "1" IS WRITTEN BY REGISTER <4201H> IS USED AS THE IN PORT. ADDRESS : $4114/$4115 NAME : *RDDIVL/*RDDIVH CONTENTS : QUOTIENT OF DIVIDE RESULT D7-D0 QUOTENT-A (LOW) 4114H D7-D0 QUOTENT-A (HIGH) 4115H THIS IS A QUOTENT (A), WHICH IS A RESULT FOR ABSOLUTE DIVIDE OF "C (16-BIT) / B (8-BIT) = A (16-BIT)". DIVIDEND (C) AND DIVISOR (B) ARE SET BY REGISTERS <4204H>-<4206H>. ADDRESS : $4216/$4217 NAME : *RDMPYL/*RDMPYH CONTENTS : PRODUCT OF MULTIPLICATION RESULT OR REMAINDER OF DIVIDE RESULT D7-D0 PRODUCT-C [MUL] / REMAINDER [DIV] (LOW) 4216H D7-D0 PRODUCT-C [MUL] / REMAINDER [DIV] (HIGH) 4217H (1) IN CASE OF MULTIPLICATION THIS IS A PRODUCT (C) WHICH IS A RESULT FOR ABSOLUTE MULTIPLICATION OF "A (8-BIT) * B (8-BIT) = C (16-BIT)". A MULTIPLICAND (A) AND A MULTIPLIER (B) ARE SET BY REGISTERS <4202H> & <4203H>. (2) IN CASE OF DIVIDE THIS IS THE REMAINDER, WHICH IS A RESULT FOR THE ABSOLUTE DIVIDE OF "C (16-BIT) / B (8-BIT) = A (16-BIT)". A DIVIDEND (C) AND DIVISOR (B) ARE SET BY THE REGISTERS <4204H><4205H> & <4206H>. ADDRESS : $4218/$4219/$421A/$421B/$421C/$421D/$421E/$421F NAME : JOY1L/JOY1H/JOY2L/JOY2H/JOY3L/JOY3H/JOY4L/JOY4H CONTENTS : DATA FOR JOY CONTROLLER I, II, III & IV D7 X BUTTON LOW D6 Y BUTTON D5 TL BUTTON D4 TR BUTTON D3-D0 ---- D7 A BUTTON HIGH D6 B BUTTON D5 SELECT BUTTON D4 START BUTTON D3 UP D2 DOWN D1 LEFT D0 RIGHT REGISTERS <4016H><4017H> CAN BE USED THE SAME AS THE FAMILY COMPUTER. 4016H-RD D0 : DATA FOR CONTROLLER I D1 : DATA FOR CONTROLLER III 4016H-WR OUT0,OUT1,OUT2 4017H-RD D0 : DATA FOR CONTROLLER II D1 : DATA FOR CONTROLLER IV NOTE: WHETHER THE STANDARD JOY CONTROLLERS ARE CONNECTED TO THE ~~~~~ SFX OR NOT CAN BE REFFERED BY READING 17TH BIT OF <4016H> AND <4017H> (SEE PAGE 22). 0: CONNECTED 1: NOT CONNECTED ADDRESS : $43X0 (X: CHANNEL NUMBER 0-7) NAME : DMAPX CONTENTS : PARAMETER FOR DMA TRANSFER D7 TRANSFER ORIGINATION DESIGNATION (SEE APPENDIX-1) TRANSFER DIRECTION A-BUS -> B-BUS B-BUS -> A-BUS DESIGNATION 0: A-BUS -> B-BUS (CPU MEMORY -> PPU) 1: B-BUS -> A-BUS (PPU -> CPU MEMORY) D6 TYPE DESIGNATION (H-DMA ONLY) ADDRESSING MODE DESIGNATION WHEN ACCESSING THE DATA (SEE APPENDIX-2). 0: ABSOLUTE ADDRESSING 1: INDIRECT ADDRESSING D5 --- D4-D3 FIXED ADDRESS FOR A-BUS & AUTOMATIC INC./DEC. SELECT. D3 0: AUTOMATIC ADDRESS INCREMENT/DECREMENT 1: FIXED ADDRESS D4 0: AUTOMATIC INCREMENT 1: AUTOMATIC DECREMENT (IN CASE "0" IS WRITTEN TO D3) D2-D0 DMA TRANSFER WORD SELECT GENERAL PURPOSE DMA: B-ADDRESS CHANGE METHOD D2 D1 D0 | ADDRESS TO BE WRITTEN --------------------------------- 0 0 0 | 1-ADDRESS 0 0 1 | 2-ADDRESS (VRAM ETC.) L,H 0 1 0 | 1-ADDRESS 0 1 1 | 2-ADDRESS (WRITE TWICE) L,L,H,H 1 0 0 | 4-ADDRESS L,H,L,H H-DMA: THE NUMBER OF BYTE TO BE TRANSFERED PER LINE AND WRITE METHOD DESIGNATION D2 D1 D0 | ADDRESS TO BE WRITTEN --------------------------------- 0 0 0 | 1-ADDRESS (1) 0 0 1 | 2-ADDRESS (VRAM ETC.) L,H (2) 0 1 0 | WRITE TWICE L,L (1) 0 1 1 | 2-ADDRESS/WRITE TWICE L,L,H,H(2) 1 0 0 | 4-ADDRESS L,H,L,H(4) ADDRESS : $43X1 (X: CHANNEL NUMBER 0-7) NAME : BBADX CONTENTS : B-BUS ADDRESS FOR DMA D7-D0 B-ADDRESS THIS IS A REGISTER, WHICH CAN SET THE ADDRESS OF B-BUS. WHETHER THIS IS THE ADDRESS OF THE "TRANSFER DESTINATION" OR THE ADDRESS OF THE "TRANSFER ORIGINATION" CAN BE DETERMINED BY D7 (TRANSFER ORIGINATION) OF REGISTER <4300H>. * WHEN THE H-DMA IS PERFORMED, IT WILL BE ADDRESS OF "TRANSFER DESTINATION". ADDRESS : $43X2/$43X3/$43X4 (X: CHANNEL NUMBER 0-7) NAME : A1TXL/A1TXH/A1BX CONTENTS : TABLE ADDRESS OF A-BUS FOR DMA D7-D0 A1 TABLE ADDRESS (LOW) 43X2H D7-D0 A1 TABLE ADDRESS (HIGH) 43X3H D7-D0 A1 TABLE BANK 43X4H THIS IS A REGISTER, WHICH CAN SET THE ADDRESS OF A-BUS WHETHER THIS IS THE ADDRESS OF THE "TRANSFER DESTINATION" OR THE ADDRESS OF THE "TRANSFER ORIGINATION" CAN BE DETERMINED BY D7 (TRANSFER ORIGINATION) OF REGISTER <4300H>. "0" SHOULD BE WRITTEN TO D7 EXCEPT A SPECIAL CASE. IN THE H-DMA MODE, THE ADDRESS OF THE TRANSFER ORIGINATION IS DESIGNATED BY THIS ADDRESS, THE DATA (APPENDIX-2) MUST BE SET BY THE ABSOLUTE ADDRESSING MODE OR THE INDIRECT ADDRESSING MODE. THIS ADDRESS BECOMES THE BASIC ADDRESS ON THE A-BUS DURING DMA TRANSFER PERIOD, AND THE ADDRESS WILL BE INCREASED OR DECREASED BASED ON THIS ADDRESS. (WHEN THE GENERAL PURPOSE DMA IS PERFORMED IT WILL BE DECREASED.) ADDRESS : $43X5/$43X6/$43X7 (X: CHANNEL NUMBER 0-7) NAME : DASXL/DASXH/DASBX CONTENTS : DATA ADDRESS STORE BY H-DMA & NUMBER OF BYTE TO BE TRANSFERED SETTINGS BY GENERAL PURPOSE DMA D7-D0 DATA ADDRESS (LOW) H-DMA 43X5H NUMBER OF BYTES TO BE TRANSFERED (LOW) GP-DMA D7-D0 DATA ADDRESS (HIGH) H-DMA 43X6H NUMBER OF BYTES TO BE TRANSFERED (HIGH) GP-DMA D7-D0 DATA BANK 43X7H IN CASE OF H-DMA THIS IS A REGISTER WHICH THE INDIRECT ADDRESS WILL BE STORED AUTOMATICALLY IN THE INDIRECT ADDRESSING MODE. THE INDIRECT ADDRESS MEANS THE DATA ADDRESS DESCRIBED ON APPENDIX-2. IT IS NOT NECESSARY TO READ OR WRITE DIRECTLY BY THE CPU EXCEPT IN SPECIAL CASES. IN CASE OF GENERAL PURPOSE DMA THIS IS THE REGISTER, WHICH CAN SET THE NUMBER OF BYTE TO TRANSFER OR TO BE TRANSFERED. HOWEVER, THE NUMBER OF BYTE "0000H" MEANS "10000H". ADDRESS : $43X8/$43X9 (X: CHANNEL NUMBER 0-7) NAME : A2AXL/A2AXH CONTENTS : TABLE ADDRESS OF A-BUS BY DMA < A2 TABLE ADDRESS D7-D0 A2 TABLE ADDRESS (LOW) 43X8H D7-D0 A2 TABLE ADDRESS (HIGH) 43X9H THESE ARE THE ADDRESSES, WHICH ARE USED TO ACCESS THE CPU & RAM, AND IT WILL BE INCREASED AUTOMATICALLY. (SEE APPENDIX-2) THE DATA OF THESE REGISTERS ARE USED AS THE BASIC ADDRESS WHICH IS THE ADDRESSS SET BY THE "A1 TABLE ADDRESS". AFTERWARDS, BECAUSE IT WILL BE INCREASED OR DECREASED AUTOMATICALLY, IT IS NECESSARY TO SET THE ADDRESS INTO THIS REGISTER BY THE CPU DIRECTLY. FOLLOWING APPLY TO H-DMA ONLY: HOWEVER, IF THE DATA WHICH IS TRANSFERED NEED TO BE CHANGED BY FORCE, IT CAN BE DONE BY SETTING THE CPU MEMORY ADDRESS TO THIS REGISTER. AND ALSO, THE ADDRESS OF THE CPU WHICH IS ACCESSED CURRENTLY WILL BE CHANGED BY READING THIS REGISTER. ADDRESS : $43XA (X: CHANNEL NUMBER 0-7) NAME : NTRLX CONTENTS : THE NUMBER OF LINES TO BE TRANSFERED BY H-DMA0;31;40m D7 CONTINUE D6-D0 NUMBER OF LINES TO BE TRANSFERED THIS IS A REGISTER WHICH SHOWS NUMBER OF LINES FOR H-DMA TRANSFER (SEE APPENDIX-2) THE NUMBER OF LINES WRITTEN TO THE CPU MEMORY WILL BE THE BASIC NUMBER OF LINE, IT IS NOT NECESSARY TO SET THE ADDRESS INTO THIS REGISTER DIRECTLY. docs/snesrom.zip0000755000000000000000000001100411266514577011123 0ustar PKm$Љ-oD& SNES-ROM.TXTZs9=Uz. lc6epM.oČ̌x_#v{{7LKztpV쑣;w51+hGB(r z\Y%1N(( վG $"*Ckó**ZmȌhBfm!V"2"1?8?` :Sb#Jv yr*3W,]}ǖRr65gsFC2ԱjGD0uQYv^i`p;QŃ.FؚLdM?.rږّb 7 Dm_ن:Tj+\ӡHr!'"Bʐf3A#l;L(4S;3Z)Ø Sp%ƒz:,&FEV~1h[Mh^O3xZd3}%xx`ĦA\ϧBZ y 3&2IgPL]~cZK,ZQSDL" b)26!WyPB܇`qg)uUMHؼ {+iZz A 3~RK8 tφ>|~ev Q@p*B(gf ~]茥S,*g#Dj?́?sMgGj@Eydz*_#xm-lΠ)ʬE~ދK3~3t5Ox}{v:H~AW`r VԼݖGپi+ƴ^E SVlDҐ_Ot!R>IJXCZrZ#?VdWgwG-8A >$37&ܯz2 bHa0LGP \=2%ׂ \d[4҉N$FSls'̸[u>] 7Qi\'kJ޻&LWRE]L3՝Qn7PkLAJ*tmq0-p7}oT"Duj$B%w ]DnQԬ O#%(:Z"-x/Ⱦp=KMkRע݂m6 aps86% K l 'yrţ\iÔѮTN:v:0bάK׿0 edL9;p_ NuЛkA€N 2&RZbza3Gd@{BdMҌ{ ʽ1Ιr^7x:dgyOe5E|u|:Ҁj]tަ|^tAϫ% Hg]k½`@oJ"ʊZe+(ձp=k yuRK(Bi$MCy-*D|L[o1Ư2F"M83% Xz%u)[[cfPh &PSx\ {˃9k5FH-6a,܉Z0G6 G+mw/9ܣūLYliڣvfl͔c}~<[ҩï%)z8::WΐN9t: !i_$=Lc.(wu}f&6x u;E4r`0֜Ҕ=Gצ;=H<Ĺws[F!vކށK1Zb)\bep3 ݋|Jk['>XX},ڴn2ddȇt%OÝ 7w^~bC,ޚn{mh9ɾ!GnZ:9\ ^|}wgR7`*eY T?@G-|0~9 &ӹoxУugnÇNڽ5xN TUwXZyomDr-B'-S-zUm6qfF$زP:]u%!y,;I:qIWF5[:t۰Zy̏Zi?:t%R:0]^vcVn"7gd@"qڨ~0 11k﹢ &Gn/}vnrobvB'2t"(~v0g7}k &ǧኇk'r6(U vIoGϡ~Z)ӱtG4#txOgÿdd^aiy`ru fz+R,J&t`!zuYZ t@#ty]o[(Q[Jcz2|s?]/h{%5.w0@23a8LGp2_rQܚњvα<5? mt8ae CkKɨ<W-<68(:O@*Ƃۙu#UBAI+ V2?sqWd+LTdO 3'S;Њ eti U^n v2,N3B/sz`MX5h6tOF+>ZTgi\Cg>Eû?`ٙ  Ej@}Hрf1̒4ԪqqM!ռm*br Ed\ ymÄ0t ?bȾCqSq1uwmS>PKm$Љ-oD&  SNES-ROM.TXTPK $sӹ  FILE_ID.DIZPKs{docs/spc-700.doc0000755000000000000000000021606411266514602010473 0ustar {\rtf1\ansi\ansicpg1250\uc1 \deff0\deflang1033\deflangfe1033{\fonttbl{\f0\froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f1\fswiss\fcharset0\fprq2{\*\panose 020b0604020202020204}Arial;} {\f16\froman\fcharset238\fprq2 Times New Roman CE;}{\f17\froman\fcharset204\fprq2 Times New Roman Cyr;}{\f19\froman\fcharset161\fprq2 Times New Roman Greek;}{\f20\froman\fcharset162\fprq2 Times New Roman Tur;} {\f21\froman\fcharset186\fprq2 Times New Roman Baltic;}{\f22\fswiss\fcharset238\fprq2 Arial CE;}{\f23\fswiss\fcharset204\fprq2 Arial Cyr;}{\f25\fswiss\fcharset161\fprq2 Arial Greek;}{\f26\fswiss\fcharset162\fprq2 Arial Tur;} {\f27\fswiss\fcharset186\fprq2 Arial Baltic;}}{\colortbl;\red0\green0\blue0;\red0\green0\blue255;\red0\green255\blue255;\red0\green255\blue0;\red255\green0\blue255;\red255\green0\blue0;\red255\green255\blue0;\red255\green255\blue255;\red0\green0\blue128; \red0\green128\blue128;\red0\green128\blue0;\red128\green0\blue128;\red128\green0\blue0;\red128\green128\blue0;\red128\green128\blue128;\red192\green192\blue192;}{\stylesheet{\widctlpar\adjustright \fs20\lang2057\cgrid \snext0 Normal;}{\*\cs10 \additive Default Paragraph Font;}{\s15\widctlpar\tqc\tx4153\tqr\tx8306\adjustright \fs20\lang2057\cgrid \sbasedon0 \snext15 footer;}{\*\cs16 \additive \sbasedon10 page number;}{\*\cs17 \additive \b \sbasedon10 Strong;}{\*\cs18 \additive \ul\cf2 \sbasedon10 Hyperlink;}}{\*\listtable{\list\listtemplateid165829716\listsimple{\listlevel\levelnfc23\leveljc0\levelfollow0\levelstartat0\levelspace0\levelindent0{\leveltext\'01-;}{\levelnumbers;}\fbias0 \fi-360\li360\jclisttab\tx360 }{\listname ;}\listid173959828} {\list\listtemplateid2019058446\listsimple{\listlevel\levelnfc23\leveljc0\levelfollow0\levelstartat3\levelspace0\levelindent0{\leveltext\'01-;}{\levelnumbers;}\fbias0 \fi-360\li360\jclisttab\tx360 }{\listname ;}\listid653531779}}{\*\listoverridetable {\listoverride\listid653531779\listoverridecount0\ls1}{\listoverride\listid173959828\listoverridecount0\ls2}}{\info{\title New Document 1}{\subject programing}{\author orynider}{\operator orynider}{\creatim\yr2004\mo4\dy8}{\revtim\yr2004\mo4\dy16\hr8} {\version14}{\edmins59}{\nofpages11}{\nofwords3553}{\nofchars20253}{\*\manager Bodin Florin Ciprian}{\*\company none}{\nofcharsws0}{\vern113}}\paperw11906\paperh16838\margl1134\margr567\margt726\margb726 \widowctrl\ftnbj\aenddoc\hyphcaps0\formshade\viewkind1\viewscale85\pgbrdrhead\pgbrdrfoot \fet0{\*\template C:\\Program Files\\Microsoft Office\\Templates\\Dot1.dot}\sectd \psz9\linex0\headery567\footery567\colsx709\endnhere\sectdefaultcl {\footer \pard\plain \s15\widctlpar\tqc\tx4153\tqr\tx8306\pvpara\phmrg\posxc\posy0\adjustright \fs20\lang2057\cgrid {\field{\*\fldinst {\cs16 PAGE }}{\fldrslt {\cs16\lang1024 11}}}{\cs16 \par }\pard \s15\widctlpar\tqc\tx4153\tqr\tx8306\adjustright { \par }}{\*\pnseclvl1\pnucrm\pnstart1\pnindent720\pnhang{\pntxta .}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang{\pntxta .}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang{\pntxta .}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang{\pntxta )}} {\*\pnseclvl5\pndec\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl8 \pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}\pard\plain \widctlpar\adjustright \fs20\lang2057\cgrid {\fs32\lang1033 SPC-700 SNES SOUND SYSTEM DOCUMENTATION }{ \i\fs32\lang1033 (v1.03 - public) \par }{\fs28\lang1033 \par }{\fs28\ul\lang1033 Disclaimer: \par \par }{\fs28\lang1033 Some of the following information was referenced with various documents and public documentation available for the SNES game console system via the World Wide Web and other user group publications. \par This document was pulled from several SNES and SPC-700 Technical Documents writen by difrent ASM coders, the rest of the content was writen by myself and my frends. \par (The rest in "Bibliografy and Acknowledgements" section). \par \par Note: In this document same info can be repeated to point another ideea. \par }{\fs28\ul\lang1033 \par }{\b\fs28\ul\lang1033 HARDWARE \par \par }{\fs28\lang1033 The SNES sound module was designed by Nintendo and manufactured by Mitsumi using a customized 16-bit processor}{\fs28\cgrid0 made by Sony specifically for the SNES. }{\fs28\lang1033 It's labeled as SPC-700. It is superior to most sound chips of its time (1991), for it has it's own memory and instruction set, which takes the load off the main CPU. \par }\pard \qj\widctlpar\adjustright {\fs28\lang1033 The SPC-700 is a co-processor. This means it is a separate separate sound module inside the SNES with its own CPU, DSP, two 32k SRAM, 2 channel 16-bit DAC, Dual Op-Amp. The main 65c816 SNES CPU co mmunicates with the SPC through four 8-bit I/O ports. When the appropriate information is sent on the I/O ports, the program in the SPC will recognize the signals and perform some action (it might be nothing at all). The SPC700 runs at a whole }{ \b\fs28\lang1033 2.048MHz}{\fs28\lang1033 , has six internal registers, and can execute }{\b\fs28\lang1033 256 opcodes}{\fs28\lang1033 . \par You cannot put a program into the SPC simply by storing it into RAM. The SPC must be sent the program via its I/O locations. When you first turn on the SNES, the SPC has an internal kernal of sorts that gives it the ability to bootstrap to a program sent over the I/O port. Provided you have such a program, you can send it to the SPC. When the SPC recieves your codes it will jump to the execution address in its memory that you specify (it's not requ ired being the start of code). This is where your program gets control of the SPC, DSP and I/O ports. \par The CPU has a built-in, small, 64 Kbyte ROM used as bootstrap code to download a more complex program and sample data from the game ROM via the 65c816. The ROM can be switched off and replaced with 64 Kbytes of RAM once the bootstrap code has done its work. \par The DSP (Digital Signal Processor) is 16-bit and supports 8 stereo channels; each independantly pannable Left to Right (8 voices). Samples sent i nto the DSP aren't the normal raw smapling used on an Amiga or PC. The samples in the SPC are encoded in a }{\b\fs28\lang1033 compressed}{\fs28\lang1033 (16-bit signet raw waveform at 14.4 KHz) format, using a custom fixed-ratio compression algorithm that compresses 16 16-bit samples into 8 bytes plus a one byte header. The designers only placed 32K of RAM into the SPC however, so the upper 32K is usualy unusable. \par The minimum unit of a sample is one }{\b\fs28\lang1033 block}{\fs28\lang1033 . The block header byte contains a shift and filter value (algorithm decompression infor mation) plus a last block flag and a loop flag; the loop flag is only used if the last block flag is also set. \par There are 8 separate sound channels allowing up to 8 samples to be played simultaneously. Each sound channel has a left and right volume setting and frequency setting. A hardware volume envelope can be defined for each channel, and echo effects can be turned on and off individually for each channel. The combined echo waveform can be subjected to an 8-tap FIR digital filter. The wave output of a ch annel can be used to modulate the frequency of the next sound channel, in numerical order. \par \par The DSP also has a white noise source that can played on a sound channel instead of sample data. All 8 channels, and any echo sound data, are mixed together and subj ected to a left and right master volume control, much like the wave table sound cards today. \par \par The DSP also provides 3 interval timers, the first two running at 8kHz and the last at 64kHz; games normally only use one of them to provide a constant music playback rate. \par \par Sound DSP chips may have a }{\b\fs28\lang1033 24.57MHz}{\fs28\lang1033 crystal on their PCB. \par \par }{\fs28\ul\lang1033 Designation & Role of Each Section}{\fs28\lang1033 : \par \par }{\b\fs28\lang1033 SPC700}{\fs28\lang1033 : SFX sound source CPU. Program an tone color dato are read into \par RAM from the casstte through the SCPU consequently controlling the game music. \par In addition, provided with an internal IPL-ROM that is activated upon rest transmission of dato though the SCPU initial settings of the SPX sound source etc, are carried out. \par \par }{\b\fs28\lang1033 DSP}{\fs28\lang1033 : Digital Signal Processor. Reproduces tone quality data in RAM. \par Possesses various functions for the purpose of musical expression. \par Programming the DSP "registers" is like programming VGA registers. \par \par 256K RAM: Shared on a time basis by the }{\b\fs28\lang1033 Sound-CPU}{\fs28\lang1033 and the DSP. \par \par }{\b\fs28\lang1033 SCPU}{\fs28\lang1033 : The CPU used for SFX. Carries out progression of the game in confomity with the cassette program. \par \par }{\b\fs28\lang1033 SPPU}{\fs28\lang1033 : PPU for SFX use. Creates imaging through CPU control. \par \par \par }{\b\fs28\ul\lang1033 SOFTWARE \par }{\fs28\ul\lang1033 \par }{\fs28\lang1033 Programing the SCP-700 on SNES is similar as programing a gived sound card chip on personal computer, to play midi, modules or mp3 in pure DOS whithout using external tsr drivers. The only thing that a programer hase to know is the CPU arhitecture. \par }\pard \widctlpar\adjustright {\fs28\lang1033 \par It operates in both 16- (Native) and 8-bit (Emulation) modes. The 8-bit emulation mode is 100% compatible with the 6502 processor in the NES system. \par }\pard \qj\widctlpar\adjustright {\fs28\lang1033 \par All program and data that is supposed to be run by SPC-700 sound chip must be' moved to the SPC's own ram with a small loop that pokes each byte of your SPC assembler program and sam ple-data into four memory locations: $2140 - $2143. They are your only chance to communicate with the SPC.}{\fs28\ul\lang1033 \par }{\fs28\lang1033 \par }{\b\fs32\ul\lang1033 WRITING A SOUND ENGINE \par }{\fs28\lang1033 \par Writing a program for the sound can be done emulating oher sound chips (like the c64-soundchip, 68000\'85) or writing a program for the spc-700 sound chip. \par \par }{\b\fs28\lang1033 GETTING A PROGRAM INTO THE SPC \par \par }{\fs28\lang1033 When the SPC starts, it waits for a startup value to appear in location 2141, this is hexadecimal $CC. However, you must do this last or else the kernal will get incorrect location and size information. Before I go too much further with this, I should ind icate the block structure the SPC recognizes as part of the transfer protocol: \par WORD Length \par WORD Location \par BYTES Data \par \par The SPC kernal will let you send any number of these blocks (ie: a MIDI implementation -or drivers- might use this to load appropriates patches for a song about to be played and then send the song - on some soundcards). \par When you've sent all blocks and want to start running code in the SPC, you send a zero-length block. There won't be any data. This block which contains only a 0 for length and a location will tell the kernal in the SPC that you're done sending and that it should jump to the program you just sent. The section below refers to this as the terminator block. \par \par }{\b\fs28\lang1033 SENDING THE BLOCKS \par \par }{\fs28\lang1033 The transfer protocol is fairly straightforward. \par Get the length and place it into a counter \par Get the location and store it to $2142-3 (a 16-bit operation will work fine). \par If this is the first chunk, place $CC into $2140 and start an 8-bit sent-count at zero. \par Send $01 to $2140 unless this is the terminator block, in which case you store a zero here. \par You send the rest of the block one byte at a time. Store the byte into $2140. \par To tell the SPC you've sent it the next value, you tell it the curent location. \par The SPC will set it to one less than the number of the curent byte sent (SPC starts this location at $FF and will wait for this location to go zero). \par Use the 8-bit sent-count. Store the sent-count to $2141 \par Wait for $2140 to mimic the value you just put into $2141. \par Please compare this with your counter and NOT the I/O port. \par Bump the sent-count \par Go back to step 5 until all bytes are sent. \par Add 3 to your sent-count \par If this makes the count 0, add 3 again. \par If this wasn't a terminator block, go back to step 4 to continue sending blocks. \par You are done and the SPC should now be doing your code. \par }{\fs26\ul\lang1033 Note}{\fs26\lang1033 : \par If speed is important, you'll want to move your blocks into RAM before sending. \par To enshore reliability during tranfers, disable the NMI while transferring blocks to the SPC. \par }{\b\fs28\lang1033 \par NEXT STEP \par }{\fs28\lang1033 \par First your program should have some means of accepting input from the SNES when it wants to change game music or play a sound effect. To do this, you need to be able to read or write values from or onto the I/O port from the SPC. On the SNES 65c816 side, the I/O ports $2140-$2143. Inside the SPC, they're zero page locations $f4-$f7. Location $f4 is $2140, $f5 is $2141, etc. So input ports at }{ \b\fs28\lang1033 $00f4/5/6/7}{\fs28\lang1033 , are }{\b\fs28\lang1033 $2140/1/2/3}{\fs28\lang1033 from the 65c816 chip! Your code will want to check these ports. Your SPC program should detect values by writing a sentinel values to the port and wait for it to change. Then call the appropriate routine or effect the appropriate chan ge. The reciever should have the task of using the sentinel to detect a change. If all the values are important, use two ports, send the byte out both ports and wait for the exclusive-or complement of the value sent to show up at one of the ports. This wi ll be the reciever telling you it has recieved the next byte ok. The reciever should wait for both locations to become equivalent before attempting to get the next byte. This will ensure the reciever that the sender has placed a value onto the port. \par }{\fs28\ul\lang1033 \par Note: \par }{\fs26\lang1033 When transmission is completed, you will also have transmitted the start address of your SPC code, and the SPC will start to execute your program there. \par \par }{\fs28\lang1033 Next, your program will want to make some noise to tell the world (and you) that it's there. To do this, you need to know about the SPC's samples and registers. I'll start with the registers, then talk about the samples. \par }{\b\fs28\lang1033 \par THE SPC-700 REGISTERS \par }{\fs28\lang1033 These registers are directly accessible from your SPC code. They are the zeropage locations $f1-$ff. \par $F1\tab SPCCON1 bits 0-2 timer enables (1=on), bits 4-5 are I/O port clear bits (11=clear all) \par \par $F2 SPCDRGA DSP Register Address latch. Write a value here to select a DSP register to read or modify. This register itself is writeonly. \par \par $F3 SPCDDAT DSP Register Data register. Read or write this register to read/write the DSP register currently referred to in SPCDRGA. \par \par $FA-$FC SPCTMLT Timer latches - place a value into the registers. The timer counts up to your time from 0. When it hits, the associated SPCTMCT register will advance. \par \par $FD-$FF SPCTMCT 4-bit counters count timer hits on each timer respectively \par Note: Timer 2 ($FC, $FF) counts at 64 kHz while the other two count at 8 kHz. \par \par }{\b\fs28\lang1033 THE SPC-700 DSP REGISTERS \par }{\fs28\lang1033 \par To store a DSP setting, you set $F2 to the DSP register address to modify and then set $F3 to the value this register is to recieve. \par \par These registers repeat for each voice (00v0), where v is a voice number from 0 to 7. \par \par 0000 Volume left \par 0001 Volume right \par 0002 Pitch low \par 0003 Pitch high (The total 14 bits of pitch height) \par 0004 SRCN Designates source number from 0-255 (sample number) \par 0005 ADSR 1 \par 0006 ADSR 2 \par 0007 GAIN Envelope can be freely designated by your code ($1f here: ignore ADSR and just output using the volume settings) \par \par 000F FILTER Filter deisgnation for this voice \par \par \par The remaining registers affect everything: \par \par 0008 ENVX Present val of envelope with DSP rewrites \par 0009 VALX Present wave height val \par 000C MASTVOLL Master volume ($7f is maximum), left channel \par 000D ECHO Echo feedback bits (1 for each voice) \par 001C MASTVOLR Master volume ($7f is maximum), right channel \par 002C ECHOVOLL Echo volume, left \par 002D PTCHMOD Pitch modulation enable bits \par 003C ECHOVOLR Echo volume, right \par 003D NOISEN Noise enable bits \par 004C KEYON Key-on (enable voice) bits \par 004D ECHOEN Echo enable bits \par 005C KEYOFF Key-off (mute voice) bits \par 005D SAMLOC Hi-byte of mem address for the sample directory table (contains start-address and loop-stars offset) \par \par 006C VOXCON Misc voice control \par Bit 7: Reset (0=off) \par Bit 6: Mute (0=off) \par Bit 5: Echo (1=off) \par \par 006D ECHOLOC Echo waveform directory location \par (Same as $5d) \par \par 007D ECHODLY Echo delay enable bits \par \par }{\b\fs28\lang1033 HOW TO DO THE MUSIC SPC-700 SAMPLE FORMAT \par }{\fs28\lang1033 \par }\pard \widctlpar\adjustright {\fs28\lang1033 The samples for the SPC are stored in a compressed (or trancripted) to a format known as }{\fs28 Bit Rate Reduction. \par }\pard \qj\widctlpar\adjustright {\fs28\lang1033 Unlike raw samples, the SPC samples are divided (or reduced) into 9-bytes bit-rate blocks, where the first byte contains header.}{\fs28\cgrid0 Each block encodes the equivalent of 16 raw 16-bit samples }{\fs28\lang1033 that can be later decompressed back, by the SPC or by the emulator, into 16 raw 16-bit samples. \par \par Data/code has to be in-groups or blocks which some call "chunks" of samples. \par \par The format for a valid chunk or block looks like that: \par \par First word: }{\b\fs28\lang1033 Number of bytes to transmit to SPC}{\fs28\lang1033 -+ \par Sec. word: }{\b\fs28\lang1033 Start address where to move data to the SPC}{\fs28\lang1033 | one chunk \par Byte 4-???? : }{\b\fs28\lang1033 Your sample/code}{\fs28\lang1033 . -+ \par \par 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ffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffff ffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffffe000ffff ffffffffffffffffffffffffffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffffe000ffffffffffffffffffff ffffffffffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffff ffffffffffffffffe000fffffffffffffffffffffffff0ffffffffffffffffffffffffffe000fffffffffffffffffffffffffe7fffffffffffffffffffffffff e000ffffffffffffffffffffffffff3fffffffffffffffffffffffffe000fe799c3ff99c3c1c1c39fff83c3e1c3fffffffffffffffffffffe000fe7999fff999 f99999f9fff9999cf9ffffffffffffffffffffffe000fe7999fff999f99999f9fff9999cf9ffffffffffffffffffffffe000fe79981ff9981c199819fff9999c f81fffffffffffffffffffffe000fe79999ff9999f999998fff9999cf99fffffffffffffffffffffe000fe79999ff9999f9999991ff9999cf99fffffffffffff ffffffffe000fe783c3ff83c3c3c1c399ff839981c3fffffffffffffffffffffe000fe79fffff9ffffff9ffffff9fffcffffffffffffffffffffffffe000f819 fffff9ffffff9ffffff9fffcffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffffe000ffffffffffffffffffff ffffffffffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffff ffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffff e000ffffffffffffffffffffffffffffffffffffffffffffffffffffe000ffffffffffffffffffffffffffffffffffffffffffffffffffffe0000400000007010100030000000000}}}{\fs28\lang1033 \cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\adjustright {\fs28\lang1033 \par rrrr - Bit 4-7 - the granularity known as "range" value (only 0-12 used), \par ff - Bit 2,3 - the filter number used (}{\fs24\lang1033 are normally zero but have significance on the LAST block}{\fs28\lang1033 ), \par l - Bit 1 - loop flag bit, \par e - Bit 0 - last block (chunk) of sample. \par \par 1). }{\fs28\ul\lang1033 THE FIRST BYTE (OR THE HEADER)}{\fs28\lang1033 \par \par \par A). }{\fs28\ul\lang1033 THE GRANULIRITY (RANGE)}{\fs28\lang1033 \par \par The }{\b\fs28\lang1033 RANGE}{\fs28\lang1033 bits tell how to read each nybble of data. Basically, you take the nybble, and you shift it left RANGE times. The nybble is signed, and this must be taken into account. Note that a }{\b\fs28\lang1033 RANGE}{\fs28\lang1033 greater than 12 would shift the nybble past a 16-bit value, so }{\b\fs28\lang1033 RANGE}{\fs28\lang1033 values from 12 to 15 is invalid. \par To }{\b\fs28\lang1033 convert}{\fs28\lang1033 a raw sample, it must first be padded to a multple of 16 and converted to a 16-bit signed waveform. The }{\b\fs28\lang1033 granularity}{\fs28\lang1033 indicates the quantization level used for this block. Higher granularity values indicate SMALLER shifts in amplitude for the BRR nybbles in this block. \par Since a nybble only has a dynamic range from -8 to 7, the granularity is used to expand this: \par }{\fs26\lang1033 \par }\trowd \trgaph108\trbrdrt\brdrs\brdrw30\brdrcf11 \trbrdrb\brdrs\brdrw30\brdrcf11 \clvertalt\clbrdrt\brdrs\brdrw30\brdrcf11 \clbrdrb\brdrs\brdrw15\brdrcf11 \cltxlrtb \cellx2263\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf11 \clbrdrb\brdrs\brdrw15\brdrcf11 \cltxlrtb \cellx6663\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 Granulirity \cell Nybbles produce dynamic range:\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\trowd \trgaph108\trbrdrt\brdrs\brdrw30\brdrcf11 \trbrdrb \brdrs\brdrw30\brdrcf11 \clvertalt\cltxlrtb \cellx2263\clvertalt\cltxlrtb \cellx6663\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 00 \cell -00008 to 00007, in steps of 0001\cell }\pard \widctlpar\intbl\adjustright { \fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 01 \cell -00016 to 00014, in steps of 0002\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright { \fs28\lang1033 02 \cell -00032 to 00028, in steps of 0004\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 03 \cell -00064 to 00056, in steps of 0008\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 04 \cell -00128 to 00112, in steps of 0016\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 05 \cell -00256 to 00224, in steps of 0032\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 06 \cell -00512 to 00448, in steps of 0064\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 07 \cell -01024 to 00896, in steps of 0128\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 08 \cell -02048 to 01792, in steos of 0256\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 09 \cell -04096 to 03584, in steps of 0512\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 10 \cell -08192 to 07168, in steps of 1024\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 11 \cell -16384 to 14336, in steps of 2048\cell }\pard \widctlpar\intbl\adjustright {\fs28\lang1033 \row }\trowd \trgaph108\trbrdrt\brdrs\brdrw30\brdrcf11 \trbrdrb\brdrs\brdrw30\brdrcf11 \clvertalt\clbrdrb\brdrs\brdrw30\brdrcf11 \cltxlrtb \cellx2263\clvertalt\clbrdrb\brdrs\brdrw30\brdrcf11 \cltxlrtb \cellx6663\pard \qj\widctlpar\intbl\adjustright {\fs28\lang1033 12 \cell -32768 to 28672, in steps of 4096\cell }\pard \widctlpar\intbl\adjustright { \fs28\lang1033 \row }\pard \qj\widctlpar\adjustright {\fs28\lang1033 \par B). }{\fs28\ul\lang1033 THE FILTERS \par }{\fs28\lang1033 \par The block can use 3 main methodes of ADPCM compression or can be uncompressed. \par There are 3 BRR filters. A filter value of zero means apply no filter. \par }{\b\fs28\lang1033 \par Filter 1}{\fs28\lang1033 : This filter is relatively simple. All you have to do, is take the 16-bit sample that was last output, multiply it by the fraction 15/16, and add the value you got by decoding the nybble as usual. In all 3 filters, this decoded value will serve as an " error" between the calculated value and the actual one. \par }{\b\fs28\lang1033 Filter 2}{\fs28\lang1033 : This filter and the next are a little more complicated. To calculate the value, multiply the last sample output by the fraction 61/32. Then, subtract from it the value when the sample before that is multiplied by the fraction 15/16. Then, add the value decoded from the nybble as always. \par }{\b\fs28\lang1033 Filter 3}{\fs28\lang1033 : This filter is identical to the last one, except the fractions are different. The fraction for the previous sample is 115/64, and for the sample before that, 13/16. \par \par C). }{\fs28\ul\lang1033 THE LOOP FLAG BIT}{\b\fs28\ul\lang1033 \par }{\fs28\lang1033 \par The loop start block - determines whether a sample will loop. So when Bit1=1 it indicates that the block is a source having a loop. \par \par D). }{\fs28\ul\lang1033 THE LAST BLOCK (CHUNK) OF SAMPLE}{\b\fs28\ul\lang1033 \par \par }{\fs28\lang1033 Determines the end of a sample. So when Bit0=1 it indicates that the block is the clock with the final data/sample. \par \par 2). }{\fs28\ul\lang1033 SAMPLES}{\fs28\lang1033 \par As you can see, the SPC uses 16-bit waveforms. There is enough space in 32K to store 58,240 samples using this compression method about 4 seconds at 14.4 KHz (sorry, the re's not quite enough space to do a real good CD quality sound track), but then there's the cartridge memory (24 MBits would hold 5.5 million samples - since the transfer gets a speed faster than playback you could double buffer and send stuff this way - this would give you about 6.5 minutes of digitized sound at CD quality in monaural recording. Stereo would halve these times). }{\fs28 So for every 32 bytes of 16-bit PCM there are 9 bytes of BRR (a compression ratio of 32:9). \par }{\fs28\lang1033 To convert you look at the raw sample 16 samples at a time. For all }{\b\fs28\lang1033 waveform points}{\fs28\lang1033 in this sample you find a range (above) that fits in all the points. This is your }{\b\fs28\lang1033 granularity}{ \fs28\lang1033 . \par \par You then use the step value to quantize each point down to one nybble. Then string these nybbles together left to right. When this is done, you just create the header byte and append the eight additional bytes from the nybbles you just obtained. This has just converted 16 bytes of your sample to BRR format ...^^ \par Repeat the above procedure for the rest of the raw sample. \par \par When recording for music, keep the }{\b\fs28\lang1033 recording rate at about 30 Khz }{\fs28\lang1033 to ensure that using the pitch value will give you a broad tonal range when using that sample as an instrument. You can forgo (skip) this rule if you're using multiple patching [re cording the instrument several times, playing the instrument at different octaves for each recording] of the instrument to counter envelope and timbre distortion (but you still have to keep this in mind however) you then match the right patch to the playb ack octave when performing music (ie: on the SPC). \par A higher recording rate gives better results after BRR conversion, as does using 16-bit samples as opposed to 8-bit samples. \par \par }{\b\fs28\lang1033 SPC-700 CODING \par \par }{\fs28\lang1033 The SPC-700 is a processor. That means that, just like the 68000, the SPC follows a program placed in its memory. This means to do music, you must either use a predefined routine from someone else or learn SPC-700 machine code. The latter isn't all th at bad (the SPC instructions set kicks butt over the 65c816's). \par There are functions for testing individual bits, changing individual bits, doing 16-bit BCD, multiplying and dividing. Additionally, there are also 16-bit instructions and the accumulator a nd Y register combine to form a 16-bit register (much like H and L on the Z80). \par The easiest way to do SPC-700 coding is with an assembler. However, there is a distinct lack of SPC-700 assemblers (as compared to 65c816 assemblers that are all over the p lace). However there are table-based assemblers (a table file is an assembler external .tab file in whitch you can change the instruction set it assembles for). \par \par }\pard \widctlpar\adjustright {\fs28\lang1033 (}{\i\fs28\lang1033 The CPU discution is avaible on the net in a detailed techincal document made by Randall Hyde on Zophar's Domain - SNES Technical Document: }{\field\flddirty{\*\fldinst {\i\fs28\lang1033 HYPERLINK "http://www.zophar.net/" }{\i\lang1033 {\*\datafield 00d0c9ea79f9bace118c8200aa004ba90b0200000003000000e0c9ea79f9bace118c8200aa004ba90b2e00000068007400740070003a002f002f007700770077002e007a006f0070006800610072002e006e00650074002f0000000000315c46004f524900434f44004d303700000000000000000000000000000000000000 0000000000}}}{\fldrslt {\cs18\i\fs28\ul\cf2\lang1033 http://www.zophar.net/}}}{\i\fs28\lang1033 )}{\fs28\lang1033 \par }\pard \qj\widctlpar\adjustright {\fs28\lang1033 Withing the CPU are the registers necessary for the execution of the various commands. \par \par For short these are an }{\b\fs28\lang1033 A}{\fs28\lang1033 register (note: functions as an 8-bit accumulator). }{\b\fs28\lang1033 X}{\fs28\lang1033 register, }{\b\fs28\lang1033 Y}{\fs28\lang1033 register (8-bit universal register which can also be used as index register). }{\b\fs28\lang1033 PSW}{\fs28\lang1033 (program status ward). }{\b\fs28\lang1033 SP}{\fs28\lang1033 (stack pointer), etc. These are all 8-bit registers but the }{ \b\fs28\lang1033 PC}{\fs28\lang1033 (program counter) is made up of 16 bits. \par \par }\pard \widctlpar\adjustright {\fs28\lang1033 Flags: N = Negative Flag; V = Overflow Flag; P = Direct Page Flag; H = Half Carry Flag; Z = Zero Flag; C = Carry Flag (Bit Accumulator); \par }\pard \qj\widctlpar\adjustright {\fs28\lang1033 \par You can get the command operand symbols and meanings from your SPC-700 assembler tutorial. \par \par }{\b\fs28\lang1033 THE DUMPED SPC FORMAT \par }{\fs28\lang1033 \par }{\b\fs28\lang1033 SPC files}{\fs28\lang1033 are save states of the Super Nintendo's sound processors during game execution in Super Nintendo emulators. When you save the song, you're mearly freezing the state of the SPC, and saving all the memory to disk. \par The game programmers can write a }{\b\fs28\lang1033 player}{\fs28\lang1033 for some }{\b\fs28\lang1033 music format}{\fs28\lang1033 that could be anything from a standard MIDI file to a proprietary format devised by the gaming company and a }{ \b\fs28\lang1033 driver}{\fs28\lang1033 for the spc-700 that could emulate oher sound chips to. \par \par So if you have a compozer and a player on your PC for a music format and you write a player for the SNES that can play more songs. Then you're playing your SNES image on your PC and you dump it to the hard drive. The dumped spc file it's }{ \b\fs28\lang1033 not}{\fs28\lang1033 the same format as the previos file that you pulled whit your compozer. }{\b\fs28\lang1033 The emulated SPC}{\fs28\lang1033 has in it's RAM some data from the songs and the program (player + driver). }{ \b\fs28\lang1033 The dumped SPC}{\fs28\lang1033 has in plus a standardized header. \par \par I did find on the World Wide Web a detalied document about the SPC file format header writen by someone (spc_file_format.txt). I do not remenber but maybe on }{\field\fldedit{\*\fldinst {\fs28\lang1033 HYPERLINK "http://www.snesmusic.org/" }{\lang1033 {\*\datafield 00d0c9ea79f9bace118c8200aa004ba90b0200000003000000e0c9ea79f9bace118c8200aa004ba90b3400000068007400740070003a002f002f007700770077002e0073006e00650073006d0075007300690063002e006f00720067002f0000000000000000000000000000}}}{\fldrslt { \cs18\fs28\ul\cf2 snesmusic.org}}}{\fs28\lang1033 ?}{\i\fs24\lang1033 \par }{\fs28\lang1033 \par There is a chance that your oryginal song to be intact in the dumped spc. If so you can make your compozer to find that in the spc file and edit. Y our songs are of course intact in the ROM image but if you edit the song directly it's a big chance that you damage the ROM. For some SNES ROM images, players and editors for SPC are released or are in development. \par \par }{\fs28\ul\cgrid0 SMAS / N-SPC MUSIC FORMAT \par }{\fs28\cgrid0 \par }{\fs28\lang1033 Some game programmers }{\fs28\cgrid0 use the same engine for many games. Most games done by Nintendo use the SMAS Engine, or N-SPC. \par }\pard \qj\nowidctlpar\adjustright {\fs28\cgrid0 \par Most games will have more than one (if not all) songs loaded into the SPC bank, there is usually a table of pointers which point to the songs in the SPC bank (starting at 100h whit the 64KB RAM). \par \par At the 0x130 in the SPC file (or 0x30 in the SPC memory) are the pointers, those are the current track counters. \par \par An N-SPC song is made up of a number of parts. \par The first is the pattern pointer list. A pattern is a collection of 1-8 tracks. Patterns can be arranged and stuff to create a song, patterns are there because of reused parts of songs etc. they will point to this pattern pointer list.}{\f1\cgrid0 }{ \fs28\cgrid0 If the song doesn't loop, the pattern pointer list end s with a 00 00. If it does, the song pointer list ends with a value less than 0100 [typically FF for most games, I personally don't think this value makes a difference, since it never has for me] (all values are stored in lil endian, reverse byte format), and then the pointer to the part of the pattern pointer list that is the loop point is placed. \par }\pard \nowidctlpar\adjustright {\fs28\cgrid0 Following a pattern pointer, you will find 8 track pointers. These are assigned to each respective DSP channel. Follow the track pointers and you're into music data. \par After the header is the data itself, At the end of a block, you can place another block header and data. After the last block you send a length of 0000 and the location is the address of the starting code in the SPC. \par \par At 0x1F6 in the SPC should be the current song number. \par \par At 0xC100 are all your song pointers. These are 16-bit each. \par \par The first pointer is for song 01, next is song 02, etc. Song 00 is nothing, as it doesn't affect anything. \par \par If your 0x1F6 is 00, then change it to a non-zero number under 0x1B ( i think that was the limit, I may be wrong), and play the song in an SPC player, it should play the song number you changed 0x1F6 to. \par \par Follow the pointer for the respective song at 0xC100, and remember, add 0x100 to the resulting address you get, because there's a 0x100-byte header tacked onto the top of SPC files.}{\f1\cgrid0 \par }{\fs28\cgrid0 \par }\pard \qj\nowidctlpar\adjustright {\fs28\cgrid0 \par \par }\pard \nowidctlpar\adjustright {\fs28\cgrid0 \par }\pard \qj\widctlpar\adjustright {\fs28\cgrid0 \par \par \par }{\fs28\ul\lang1033 DEVELOPMENT TOOLS}{\fs28\lang1033 : \par \par DSPC - A SPC700 Disassembler, \par SNES debugger, Jeremy Gordon's 65816, \par Famidev TASM + table instruction set by Gau of the Veldt, \par The Telemark Assembler (TASM) v3.2 + table instruction set by }{\field\fldedit{\*\fldinst {\fs28\lang1033 HYPERLINK "mailto:minus@infomatch.com"}{\lang1033 {\*\datafield 00d0c9ea79f9bace118c8200aa004ba90b0200000003000000e0c9ea79f9bace118c8200aa004ba90b360000006d00610069006c0074006f003a006d0069006e0075007300400069006e0066006f006d0061007400630068002e0063006f006d000000000000000000000000000000000000000000000000}}}{\fldrslt { \cs18\fs28\cf2 Minus}}}{\fs28\lang1033 , \par Some SPC-700 and SNES Assemblers, \par Total Recorder v3.x - High Criteria Inc, \par }\pard \widctlpar\adjustright {\fs28\lang1033 Cool Waveform Editor (Cool Edit version 1.21 or higher), \par }\pard \qj\widctlpar\adjustright {\fs28\lang1033 GoldWave v2.11 or higher - Chris Craig. \par \par }{\fs28\ul\lang1033 Bibliografy and Acknowledgements: \par }{\fs28\lang1033 \par }{\i\fs28\lang1033 Gau of the Veldt}{\fs28\lang1033 : }{\i\fs28\lang1033 SPC 700 Documentation}{\fs28\lang1033 , \par }{\i\fs28\lang1033 Antitrack}{\fs28\lang1033 : }{\i\fs28\lang1033 The Bloody SPC-700 }{\fs28\lang1033 from}{\i\fs28\lang1033 Yoshi's}{\fs28\lang1033 : }{\i\fs28\lang1033 SNES Documentation v2.30, \par Randall Hyde}{\fs28\lang1033 : }{\i\fs28\lang1033 SNES Technical Document}{\fs28\lang1033 , \par }{\i\fs28\lang1033 Ledi}{\fs28\lang1033 : }{\i\fs28\lang1033 Apu Manual }{\fs28\lang1033 (1997), \par }{\i\fs28\lang1033 Zophar's Domain TM, \par }{\i\fs28\cgrid0 Bouch\'e9 (Andrew Lim): N-SPC format, \par Acmlm's Board.}{\i\fs28\lang1033 \par }{\fs28\lang1033 \par (If someone is left out please e-mail me to: }{\field\fldedit{\*\fldinst {\fs28\lang1033 HYPERLINK "mailto:orynider@rdslink.ro"}{\lang1033 {\*\datafield 00d0c9ea79f9bace118c8200aa004ba90b0200000003000000e0c9ea79f9bace118c8200aa004ba90b360000006d00610069006c0074006f003a006f00720079006e00690064006500720040007200640073006c0069006e006b002e0072006f0000000000434f440000000000000000000000000000000000000000000000 00}}}{\fldrslt {\cs18\fs28\ul\cf2 orynider@rdslink.ro}}}{\fs28\lang1033 ) \par If you would like to add any info releated to this contact-me or send-me the updated document. If you use content writen by others let me know they names! \par \par OryNider - 2004 \par This file was downloaded from: }{\field\flddirty{\*\fldinst {\fs28\lang1033 HYPERLINK "http://pubory.3x.ro/pub/nintendo/docs/index.html"}{\lang1033 {\*\datafield 00d0c9ea79f9bace118c8200aa004ba90b0200000003000000e0c9ea79f9bace118c8200aa004ba90b6200000068007400740070003a002f002f007000750062006f00720079002e00330078002e0072006f002f007000750062002f006e0069006e00740065006e0064006f002f0064006f00630073002f0069006e006400 650078002e00680074006d006c000000000020202000202020000000000000000000000000000000000000000000000000}}}{\fldrslt {\cs18\fs28\ul\cf2\lang1033 http://pubory.3x.ro/pub/nintendo/docs/index.html}}}{\fs28\lang1033 \par }}docs/spc.txt0000755000000000000000000000366211266514602010237 0ustar From: D Burton Technician To: "Super Famicom Development Group" Subject: Re: sound Date: Fri, 17 Dec 93 09:37:41 GMT > Any info on the structure & size of the header block? > the header is as follows :- dw length_of_block,transfer_address db start_of_data ..... db end_of_data this is repeated for however many blocks u wanna load into the spc(often just one big block) then the final header reads:- dw $0000,program_execution_address the zero length field tells it to get ready to run the module.. > So the data is broken up into 9 byte blocks then. How is this 1 byte range > related to the data that follows? Is it a multiplier or, exponent or > value from a table? The 4 bit data an 'error' relative to the range? > Any other info on the samples? > the first byte contains :- bit 0 - last block of sample bit 1 - loop block flag bit 2,3 - the filter number used bit 4-7 - the range value (only 0-12 used).. the big question is how is the data compressed - the manual diagram simply shows the 4 bit data being shifted right by the range number of places, and then talks of the number being in the range -7 to +8.. I have been simply dividing the 16 bit numbers down and rounding up where necessary and this gives a quite accurate conversion, the problem I seem to be having is generating the range values from the 16 values I have.. > I checked out hbt-fasm, which someone described as bad. Does bad refer to > its interface or the fact that it doesn't disassemble things correctly? > I do not have access to the spc-700 instruction set, or an amiga on a > regular basis and will build an opcode matrix from it and convert it to > the pc (providied that it disassembles correctly). Does it?. > I have not had much to do with hbt-fasm so dont really know what is wrong with it, my own SPC dissassembler has no real super duper i/face, but it does what I wanted it to. docs/spc2.txt0000755000000000000000000000530111266514603010312 0ustar From: lca@gnu.ai.mit.edu (.oO| Spaceman Spiff |Oo.) To: "Super Famicom Development Group" Subject: Re: Samples on de SNEZ Date: Tue, 11 Jan 94 14:34:35 EST > > > A while back someone mentioned that the SPC700 chip was the same sound chip > as in the <****> computer (forget which one), and that they had made a > really simple disassembler for it. If someone could point me towards any > docs (books) on the spc700, or possibly if it isn't too much trouble, the > intruction set of the spc700 I would appreciate it.... I'm not looking for > "programming the spc700 on the snes" Maybe just a <****> book with a chapter > on programming sound using the spc700.... I realize that no one person out > there knows how to do the music, sample formats, etc, but I think if we had > a spc700 disassembler that a couple of us so inclined could start to work > on the whole sound driver problem.... > > thanks in advance.... > > -jeremy > > Welp music doesn't seem to be too bad. There is a really good musik ripper on rhe Amiga that rips music out of SMC or BIN formats. I forgett the name, since I don't have an Amiga :( .. oh well .. anyhoo here is some sample source for playing a .SPC on the spc700 in the snez .. it's pretty choppy but it's what I use. REP #$30 ; X,Y FIXED -> 16 BIT MODE SEP #$20 ; ACCUMULATOR -> 8 BIT MODE LDA #$00 JSL $1C8000 LDA #$01 JSL $1C8000 LDA #$17 LDY #$0001 JSL $1C8000 LDA #$13 LDY #$003F JSL $1C8000 LDY #$0004 ;<- Here Change your favourite TECHNO MuZaK JSL $1C8000 ... ... ... ;<- Here Your Source! ... ... ... ORG $1C8000 MUSIC .BIN C:\SNEZ\DEMUZAK.SPC -=-=-=-=-=-=-=-=-=-=-= or you could do it this way -=-=-=-=-=-=-=-=-=-=-= PHB REP #$30 ;A,X,Y 16 BIT JSL $1F8000 PLB PHB REP #$30 ;A,X,Y 16 BIT LDA #$01 ;<- CHANGE MUSIC JSL $1F8004 LDA #$C0 JSL $1F8008 PLB CLC JSL $1F8014 ;STOP MUSIC ORG $1B8000 .BIN C:\SNEZ\DEMUZIK.SPC -=-=-=-=-=-=-=-= Anhyhoo .. that's the same shit but a little clearer. Now the only propblem with all this is you can't use your own musak .. 'cuz I don't know anyonwe who knows the format or even if a composer exists. But, my original post refered to samples and sound effects. 'cuz I don't knowe ANYONE wjho knows who those work 100% .. oh well .. ttyl -=SPiFF=- docs/spcTodo.txt0000755000000000000000000026503211266514605011071 0ustar ====================================================================== APU MANUAL IN TXT BY LEDI. (1997) ====================================================================== TABLE OF CONTENTS 1. SFX Sound Source Outline 1.1. SFX Sound Source Outline 1.2. System Outline 1.3. Memory Mapping 1.4. Signal Flow. 2. I/O Ports 2.1. Peripheral Function Registers 2.2. Functions 3. Control Register 3.1. Port Clearing 3.2. Timer Control 4. Timers 4.1. Explantion of Functions 4.2. Timer Action 4.3. Related Registers 5. DSP Interface Register 6. DSP Registers 6.1. Register RAM Map 6.2. Register Functions 6.3. Source Specifications 7. CPU Organization 7.1. CPU Registers 7.2. Memory Space 8. Appendix No.1. Support Tools 9. Appendix No.2. Summary of SPC700 Commands SFX SOUND SOURCE OUTLINE 1.1. OUTLINE The SFX sound source is composed of a Sound-CPU-IC a single chip in which are integrated an 8 bit CPU, IPL ROM, I/O ports and timers, and DSP-IC and peripheral apparatus. CHARACTERISTICS * CPU : Sony SPC700 series CMOS 8-bit CPU core * Minimum Command Execution Time : 1.953 microS/2.048MHz when active * Intenal ROM : 64 byte (IPL ROM) * Memory Space : 64K byte * Peripheral Functions * I/O Ports : SCPU Interface I/O Ports 8 bit x4 Universal I/O Ports 8 bit x 2 * Timers : (8 bit timer + 4 bit counter) x3 sets * Output Sound Production : 4-bit ADPCM sampling sound x 8 tones (simultaneous production) 1.2. SYSTEM OUTLINE ( Un dibujo sobre la consola, la APU y el DSP. ) Designation & Role of Each Section: Sound-CPU: SFX sound source CPU. Program an tone color dato are read into RAM from the casstte through the SCPU. consequently controlling the game music. In addition, provided with an internal IPL-ROM which is activated upon rest transmission of dato though the SCPU initial settings of the SPX sound source etc, are carried out. DSP: Digital signal processor. Reproduces tone quality data in RAM. Possesses various functions for the purpose of musical expression. 256K RAM : Shared on a time basis by the Sound-CPU and the DSP. SPCU : CPU for SFX use. Carries out progression of the game in confomity with the cassette program. SPPU : PPU for SFX use. Creates imaging through CPU control. 1.3. MEMORY MAPPING 0000H -------------------- | | | External | | Memory | | Region | 0-Page 00EFH | | -------------------- 00F0H | | | Pheripheral | | Function | | Registers | | | 00FFH | | -------------------| 0100H | | | External | | Memory | 1-Page | Region | | | 01FFH | | -------------------| 0200H | | | | | | | | | External | | | | Memory | | | | Region | | | | | | | 7FFFH | | -------------------| | | | | | | | Unusable | | | | | FFBFH | | -------------------| FFC0H | | | IPL ROM 64 bytes| | (*) | FFFFH | | -------------------- * The initial hardware setting program is installed in the IPL ROM. (Un Dibujo sobre el flujo de datos.) 2. I/O PORTS 2.1. PERIPHERAL FUNCTIONS REGISTERS Peripheral Function Registers Address Function Register R/W When Reset Remarks 00F0H (test) --- ------ Installed in sound-CPU 00F1H Control W Control = "00-000" 00F2H Register Add. R/W Indeterminate Installed in DSP 00F3H Register Data R/W Indeterminate Installed in DSP 00F4H Port-0 R/W Port0r = "00" Installed in sound-CPU Port0w = "00" 00F5H Port-1 R/W Port1r = "00" Installed in sound-CPU Port1w = "00" 00F6H Port-2 R/W Port2r = "00" Installed in sound-CPU Port2w = "00" 00F7H Port-3 R/W Port3r = "00" Installed in sound-CPU Port3w = "00" 00F8H ------ --- ---------- ------------------- 00F9H ------ --- ---------- ------------------- 00FAH Timer-0 W Indeterminate Installed in sound-CPU 00FBH Timer-1 W Indeterminate Installed in sound-CPU 00FCH Timer-2 W Indeterminate Installed in sound-CPU 00FDH Counter-0 W Indeterminate Installed in sound-CPU 00FEH Counter-1 W Indeterminate Installed in sound-CPU 00FFH Counter-2 W Indeterminate Installed in sound-CPU 2.2 APU I/O PORTS Ports 0-3 are ports which carry out data transmission to the SPCU through the SPX bus and are composed of four 8-bit inport registers and four 8-bit outport registers. Port nr registers can only write from the SPCU section and can only read from the Sound-CPU section. The opposite is true of the port nw registers. Since the composition of each of these ports is identical, an explanation will be made using Port Or and Port Ow as examples. 1. Data is input into Port Or when the SCPU writes data into 2140H. Then the contents of Ports Or are read when the Sound-CPU reads the data in 00F4H ( this is also true of Ports 1r - 3r). 2. Data is written into Port Ow when the Sound-CPU writes data into the APU I/O port (00F4H). Then the contents of Port OW are read when the SCPU reads 2140H ( this is also true of Ports 1w-3w). 3. When reset is carried out, the contents of Port nr registesr and Port nw registers become "00" (n=0-3) Table 2.1.1. Port0 - Port3 Registers Address Seen Address Seen Register Name W/R Function Seen From From Sound-CPU From SCPU Sound-CPU Section 00F4H 2140H Port0r R Read content of Port0r reg. Port0w W Write to Port0w reg 00F5H 2141H Port1r R Read content of Port1r reg. Port1w W Write to Port1w reg 00F6H 2142H Port2r R Read content of Port2r reg. Port2w W Write to Port2w reg 00F7H 2143H Port3r R Read content of Port3r reg. Port3w W Write to Port3w reg Fig 2.2.1. I/O Diagram from SCPU to SCPU | | Port nr | Port nw | ----------------- ----------------- | | | | | | | | | | | | | | | | | | ----------------- ----------------- | | | | to Sound-CPU from Sound CPU 3. CONTROL REGISTER 3.1. THE PORT CLEAR FUNCTION BY MEANS OF THE CONTROL REG. The ports are cleared to 00 when 1 is written into the Control register port clear control bits PC32 PC10. When 0 is written in, they are not cleared. When 1 is written into the port clear control bit PC10, both the port 0r register and the port 1r register are cleared to 00. In the same manner, when 1 is written in PC32 both the port 2r register and the port 3r register are cleared to 00. Control Register D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------- Control | -- | -- |PC32|PC10| -- | ST2| ST1| ST0| (W) (00F1H) ----------------------------------------- | | 1 Port Reset ------------------- 0 No Clear When Reset: "--00-000" Note : Clear Timing Port clear is executed during the machine cycle following that in which 1 is written into the port clear control bit. When port clear timings conflicts with write timing to the port in question from the SFX bus, there are cases in which the contents of the register in question become indeterminate. | Machine Cycle | Machine Cycle | --------------- --------------- | / | | / Clear Pulse ----------/---------- -------- / | | ---- Timings when 1 is written into the port clear control bit. 3.2. TIMER CONTROL BY MEANS OF THE CONTROL REG Control Register D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------- Control | -- | -- |PC32|PC10| -- | ST2| ST1| ST0| (W) (00F1H) ----------------------------------------- | | 1 Port Reset ------------------- 0 No Clear When Reset: "--00-000" ST0 is the Timer TO start/stop control bit the timer stops with 0 and starts with 1. At this timer, it is necesary to input 1 into ST0 once it has been changed to 0. ST1 and ST2 are respectively the start/stop control bits of timers T1 and T2. Their function is identical to that of ST0. NOTE : In regard to the timers, please see next section. 4. TIMERS 4.1. FUNCTION OF TIMERS T0, T1, T2 The SFX sound source is provided with three timers T0, T1 and T2. Clock 2.048Mhz ----> Prescaler 8 bits | | | | | | 8KHz Lower level 8-bit Upper level 4-bit | ------ programmable up counter T0 | | interval timer. | | | | 8KHz | ------ Save as above Same as above T1 | | 64KHz --------------- Save as above Same as above T2 Fig. 4.1. Timer Section The timers T0, T1 and T2 are each composed of a lower level 8-bit programmable interval timer connected to a upper level 4-bit up counter. The 8-bit timer is made up of an 8-bit binary up counter, comparator, timer register and control circuit; and each of the timers T0, T1 and T2 is independently programmable. The clock input to timers T0 and T1 from the prescaler is 8KHz ( 125 microS) and that to timer T2 from the prescaler is 64KHz (15.6 microS). Table 4.1. Timer Function ------------------------------------------------------------------- | 8-bit Timer | 4-bit Up Counter | ------------------------------------------------------ | Resolution | Max. Count Value | Max Count Value | ------------------------------------------------------------------- Timer T0, T1 | 125 microS | 32miliS | 512miliS | ------------------------------------------------------------------ Timer T2 | 15.6 microS | 4miliS | 64miliS | ------------------------------------------------------------------- 4.2. TIMER ACTION Since each timer T0, T1 and T2 is structured identically, explanation will be made taking timer T0 as an example. The lower level 8-bit timer of timer T0 is composed principally of a binary up counter, which is incremented at each count clock input. When its value corresponds to the contents of the timer register. it is cleared to 00H. Simultaneously a pulse is generated to the 4-bit up counter. The 4-bit up counter is composed principally of a binary up counter, which increments at each input of a lower level pulse. The action of the counter of timer T0 is controlled by the 0 bit of the control register. When bit ST0 is 0 count up is suspended. Count up commences when both upper level and lower level counters are cleared by "1". Consequestly, in order to clear the counters, it is necessary to set bit ST0 to "1" after having once set it to "0". Writing into the timer register is carried out while the counter is stopped. At this time, the minimun value of the write values is 01H and the maximun values is 00H. Though it is not possible to read the value of the timer register, it is possible to read the 4-bit values CN0 at any time. When the values of CN0 is read, only the 4-bit up counter section is cleared to "00". Upper Level 4-bit Counter Timing 4-bit Counter ----------------- | | Pulse -----| CN | CK -----| | ----------------- | - | | | | - ----- | |---------- Read Clear Pulse --- Action of timer T0 is stopped by means of the reset input ( POR = "1"). At this time of reset ST0 of the control register is "0", and CN0 and TN0 of the timer register are indeterminate. when CN is read, the 4-bit up counter alone is cleared through .. internal timing, but the read clear pulse and the pulse to the 4-bit up counter do not conflict with each other. Consequently, when the pulse is input to the 4-bit up counter, the values of CN will necessarily be incremented or when value of CN is read. CN will be cleared and CN will become "0". Internal Signal - ------ ------ -- // - ------ --- | | | | | | | | | | - - - - - - | | Read Clear Pulse --|--------|--- --|---- // -|--------|------ | - | | - | | | | | Pulse to 4 bit --|--------|----- |---- // -|----- |------ Counter / | | | | / / | /| Value of CN ----- 4 --------|0 |--------------/-| 2 | / | | / Read Value of CN Read Value de CN Value is 1. Value is 2. 4.3 TIMER RELATED REGISTERS Control Register D7 D6 D5 D4 D3 D2 D1 D0 Control ------------------------------------------- (00F1H) | -- | -- |PC32|PC10| --| ST2 | ST1 | ST0 | (W) ------------------------------------------- | | | | | | 1 Timer Start | | | ---------------- 0 Timer Stop When Reset: "--0-000" Timer Register D7 D6 D5 D4 D3 D2 D1 D0 --------------------------------- Timer-0 | TM0 | (W) (00FAH) ---|---|---|---|---|---|---|----- Timer-1 | TM1 | (W) (00FBH) ---|---|---|---|---|---|---|----- Timer-2 | TM2 | (W) (00FCH) ---|---|---|---|---|---|---|----- Counter Register D7 D6 D5 D4 D3 D2 D1 D0 --------------------------------- Counter-0 | ----------- | CN0 | (R) (00FDH) | | | |---|---|---|---|---|---|---|---| Counter-1 | ----------- | CN1 | (R) (00FEH) | | | |---|---|---|---|---|---|---|---| Counter-2 | ----------- | CN2 | (R) (00FFH) | | | |---|---|---|---|---|---|---|---| Indeterminate when Reset 5. DSP INTERFACE REGISTER. Interface register D7 D6 D5 D4 D3 D2 D1 D0 ------------------------------- Register Add.| Register Address | (R/W) (00F2H) | | ---|---|---|---|---|---|---|--- D7 D6 D5 D4 D3 D2 D1 D0 ------------------------------- Register Add.| Register Address | (R/W) (00F3H) | | ---|---|---|---|---|---|---|--- Indeterminate When Reset This is the register which sets data into the registers within DSP. Values are set the designated register in accordiadance with the course of the flow-chart below. i) The DSP addess to be set is written into 00F2H. ii) Data is written intro 00F3H. When the content of the register data is to be read, it also follows the flow-chart below i) The address to be read if set in 00F2H. ii) The content of 00F3H is seen. Setting data into Reading data in DSP registers DSP registers /--------------\ /--------------\ | Address is | | Address is | | set on 00F2H | | set on 00F2H | \--------------/ \--------------/ | | | | | | | | \|/ \|/ /-------------\ /-------------\ | Data is set | | Address is | | in 00F3H | |seen in 00F3H| \-------------/ \-------------/ | | \|/ \|/ Secondary Secondary Processing Processing 6. REGISTER USED 6.1. DSP REGISTER MAP. Address Register Explanation of Function -------------------------------------------------------------------- 00 VOL (L) \ left and right volume 01 VOL (R) / 02 P (L) \ The total 14 bits of P(H) & P(L) express 03 P (H) / pitch height 04 Voice 0 SRCN Designates source number from 0-256 05 ADSR (1) \ Address is designated by D7 = 1 of ADSR(1): 06 ADSR (2) / when D7= 0 GAIN is operative. 07 GAIN Envelope can be freely designated by the program. 08 *ENVX Present value of evelope which DSP rewrittes at each Ts. 09 *OUTX Value after envelope multiplication & before VOL multiplication (present wave height value) ----------------------------------------------------------------------- 10-19 Voice 1 : \ 20-29 Voice 2 : | 30-39 Voice 3 : | 40-49 Voice 4 : | Same as Voice 0 50-59 Voice 5 : | 60-69 Voice 6 : | 70-79 Voice 7 : / ----------------------------------------------------------------------- 0c MVOL (L) Main Volume (L) 1c MVOL (R) Main Volume (R) 2c EVOL (L) Echo Volume (L) 3c EVOL (R) Echo Volume (R) 4c KON Key On. D0-D7 correspond to Voice0-Voice7 5c KOF key Off. 6c FLG Designated on/off of reset, mute, echo and noise clock. 7c *ENDX Indicates source end block. ---------------------------------------------------------------------- 0d EFB Echo Feed-Back 1d --- Not Used 2d PMON Pitch modulation of Voice i with OUTX of Voice (i=1) as modulated wave. 3d NOV Noise on/off. D0-D7 correspond to Voice0-Voice7 4d EOV Echo On/Off 5d DIR Off-set address of source directory 6d ESA Off-set address of echo region. Echo Start Address 7d EDL Echo Delay. Only lower 4 bits operative. ----------------------------------------------------------------------- 0f C0 \ 1f C1 | 2f Filter C2 | 3f Coefficients C3 | Echo Filter coefficients 4f C4 | Makes up an 8 tap FIR Filter 5f C5 | (Both L & R have the same filter ). 6f C6 | 7f C7 / ---------------------------------------------------------------------- * Register intro which DSP writes in conditions of activity. 6.2. REGISTER FUNCTION 6.2.1. Register of each Voice ( Addresses indicated are those of Voice0) (1) VOL(L), VOL(R) D7 D6 D5 D4 D3 D2 D1 D0 --------------------------------- VOL(L) |sign| VOL (L) | (00H) | | | |----|---|---|---|---|---|---|---| VOL(R) |sign| VOL (R) | (01H) | | | |----|---|---|---|---|---|---|--- Each is a volume multiplied by Lch and Rch, and is in a 2's complement form. making D7 the sign bit. When a negative value is entered phases reverse. (2) P(L), P(H) D7 D6 D5 D4 D3 D2 D1 D0 -------------------------------- P(H) |(0) (0)| P(H) | (02H) | | | |---|---|---|---|---|---|---|---| P(L) | P(L) | (03H) | | |---|---|---|---|---|---|---|---- Pitch is expressed by the total fouteen bits combining six lower level bits of P(H) and eight bits of P(L). At this time two upper bits of P(H) are invalid. ( Considered to be "0" at all times ). With f as the frequency of the reproduced sound, f0 ( f sub zero ) as the frequency of the original sound (sound at the time of recording), and p as the value expressed by the upper level fourteen bits of P(H) and P(L), the following formula is formed : P f = f0 * ---- 12 2 The diagram below illustrates the relationship between p and the octaval ratio of the reproduced sound and the original sound. There are theoretically no limitations in the practical range so long as the original sound is converted lower, however, when converted higher, only up to approximately four times the frequency of the original sound can be accomodated. Interval: -2oct -1oct original +1oct +2oct (approx) -----|--------|-------|----------|-------| 0400H 0800H 1000H 2000H 3FFFH In terms of tone quality, the lower level 4 bits of P(L) should be set at 0 when possible in cases where pitch aberrations are not of concern. (3) ADSR(1), ADSR(2) D7 D6 D5 D4 D3 D2 D1 D0 ---------------------------------- ADSR(1) |ADSR | DR | AR | (05H) |/GAIN| | | |-----|---|---|---|---|---|---|---| ADRS(2) | SL SR | (06H) | | |-----|---|---|---|---|---|---|---- When D7 of ADSR(1) =1, these two bytes become operable ( ADSR mode) AR is multiplied by the fixed value 1/64 and DR, SR by the fixed value 1-1/256. When in the state of "key off". the "click" sound is prevented by the addition of the fixed value 1/256 (GAIN mode is identical). TABLE 6.2. ADSR parameters |AR Time 0 to 1|DR|Time 1 to SL|SL|Ratio| SR Time 1to 1/10| --------------------------------------------------------------------- |0 | 4.1 sec | 0| 1.2 sec | 0| 1/8 | 0| INF |10|1.2 sec |1 | 2.6 | 1| 740 msec | 1| 2/8 | 1| 38 |11|880 msec |2 | 1.5 | 2| 440 | 2| 3/8 | 2| 28 |12|740 |3 | 1.0 | 3| 290 | 3| 4/8 | 3| 24 |13|590 |4 |640 msec | 4| 180 | 4| 5/8 | 4| 19 |14|440 |5 |380 | 5| 110 | 5| 6/8 | 5| 14 |15|370 |6 |260 | 6| 74 | 6| 7/8 | 6| 12 |16|290 |7 |160 | 7| 37 | 7| 1 | 7| 9.4 |17|220 |8 | 96 -------------------------- 8| 7.1 |18|180 |9 | 64 | | 9| 5.9 |19|150 |A | 40 | | A| 4.7 |1A|110 |B | 24 | | B| 3.5 |1B| 92 |C | 16 | | C| 2.9 |1C| 74 |D | 10 | | D| 2.4 |1D| 55 |E | 6 | | E| 1.8 |1E| 37 |F | 0 | | F| 1.5 |1F| 28 --------------- --------------------------- (There is a possibility that parameter values muy vary) | | 1 |-------- | /\ | /| \ | / | \ | / | \ SL|---/---|-----\ | / | | \ \ | / | | \ \ \ \ \ \ \ \ |/AR | DR | SR | \ t |------------------------------------------- 0 | key on Key off (4) GAIN This becomes operable when D7 of ADSR(1) = 0. The following five modes are available. D7 D6 D5 D4 D3 D2 D1 D0 -------------------------------- Direct Designation | | | (07H) | 0 | | |---|---|---|---|---|---|---|---| -------------------------------- Increase Mode | | | | | (linear ) (07H) | 1 | 1 | 0 | | |---|---|---|---|---|---|---|---| -------------------------------- Increase Mode | | | | | (Bent line ) (07H) | 1 | 1 | 1 | | |---|---|---|---|---|---|---|---| -------------------------------- Decrease Mode | | | | | (linear ) (07H) | 1 | 0 | 0 | | |---|---|---|---|---|---|---|---| -------------------------------- Decrease Mode | | | | | (exponential)(07H) | 1 | 0 | 1 | | |---|---|---|---|---|---|---|---| * Direct Designation : The value of GAIN is set directly by the values of D0-D6 * Increase (linear) : Addition of the fixed value 1/64. * Increase (bent line): Addition of the constant 1/64 up to 0.75 of the constaint 1/256 from 0.75 to 1. * Decrease (linear) : Subtraction of the fixed value 1/64. * Drecrease (exponential) : Multiplication by the fixed value 1-1/256. In all cases present envelope values (values indicatdby ENVX) are utilized for initial values. 1.00 |- - - - - - ------------------------ | / / | / / | / / 0.75 |- - -// | / / x | / / Curve = 1-ke | / / |/ / |---------------------------------------- x Increase Mode : 1-ke is approximated with bent lines. The various parameter values are indictad on the next page. GAIN PARAMETERS Parameter Increase Mode Increase Mode Decrease Mode Decrease Mode Values linear (0->1) bentline (0->1) linear (1->0) exponential (0->1/10) ------------------------------------------------------------------------ 00 INF INF INF INF 01 4.1 7.2 4.1 38 02 3.1 5.4 3.1 28 03 2.6 4.6 2.6 24 04 2.0 3.5 2.0 19 05 1.5 2.6 1.5 14 06 1.3 2.3 1.3 12 07 1.0 1.8 1.0 9.4 ------------------------------------------------------------------------- 08 770 msec 1.3 770 msec 7.1 09 640 1.1 640 5.9 0A 510 900 msec 510 4.7 0B 380 670 380 3.5 0C 320 580 320 2.9 0D 260 450 260 2.4 0E 190 340 190 1.8 0F 160 280 160 1.5 ------------------------------------------------------------------------- 10 130 220 130 1.2 11 96 170 96 880 msec 12 80 140 80 740 13 64 110 64 590 14 48 84 48 440 15 40 70 40 370 16 32 56 32 290 17 24 42 24 220 ------------------------------------------------------------------------- 18 20 35 20 180 19 16 28 16 150 1A 12 21 12 110 1B 10 18 10 92 1C 8 14 8 74 1D 6 11 6 55 1E 4 7 4 37 1F 2 3.5 2 18 ------------------------------------------------------------------------- (5) SRCN Refers to Source Number. It is the sequence of tone color within the hexa-file of tones produced by means of a separate tool. (0-255). D7 D6 D5 D4 D3 D2 D1 D0 -------------------------------- SCN | | (07H) | | |---|---|---|---|---|---|---|---| (6) ENVX The present value of the ADSR/GAIN envelope constant. The DSP section rewrites this at each Ts (31.25 microseg). Seven bits without a sign bit. (D7 is always 0) D7 D6 D5 D4 D3 D2 D1 D0 -------------------------------- ENVX | | | (08H) | 0 | | |---|---|---|---|---|---|---|---| (7) OUTX The present value of the wave height after envelope multiplication and prior to VOL multiplication. DSP section rewrites this at each Ts (31.25 microseg). 8 bits with sign bit, its value is utilized as the modulated wave of pitch modulation. D7 D6 D5 D4 D3 D2 D1 D0 --------------------------------- OUTX | | | (09H) |Sign| | |----|---|---|---|---|---|---|---| 6.2.2. COMPLETE VOICE REGISTERS (1) KON, KOF "Key on" and "Key off". D0-D7 correspond to Voice 0-7. When "1", key on or key off are carried out ; when "0", neither is carried out. These two registers need not be reset. With KOF, in regard to any Voice in which "1" is written, whether in the ADSR mode or GAIN mode, 1 to 0 decreases at the rate of 8 nsec by means of the addition of the fixed value 1/256. In writing in a succession of KON and KOF. two Ts (62.4 microsec) or more should be released. (In writing in a sucession of various data in less than two Ts, the data written in may not be operable later.) D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------------------------------- KON |Voice 7|Voice 6|Voice 5|Voice 4|Voice 3|Voice 2|Voice 1|Voice 0| (4CH) ----------------------------------------------------------------- D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------------------------------- KOF |Voice 7|Voice 6|Voice 5|Voice 4|Voice 3|Voice 2|Voice 1|Voice 0| (5CH) ----------------------------------------------------------------- (2) PMOD Pitch modulation is imposed on Voice i with OUTX of Voice(i-1) (i=1-7) as a modulated wave. When Di = 1 it becomes modulation OX. ( For example when D1=1, a modulated tone issues from Voice 1). However modulation does no affect Voice0. Therefore, the bit D0 is not operable. In regard to the method of pitch modulation, when y0 ( y sub zero ), is the wave height value of the modulated wave and P is the value of P(H) and P(L), then : x P = P (t+y ) 0 x The values of P as above takes the place of P and is utilized as the values of the picth at that time. D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------------------------------- PMOD |Voice 7|Voice 6|Voice 5|Voice 4|Voice 3|Voice 2|Voice 1| ----- | (2BH) ----------------------------------------------------------------- (3) NON Noise on/off. D0-7 correspond to Voice 0-7. When on noise is issued instead of sound source data. At this time, if sound source data of formants only is designated through the previous SRCN, then noise is produced only for the length of time of the sound source data. When reproduction for random lengths of time is desired, sound source data incorporating a loop must necessarily be designated through SRCN. In Addition even though two o more voices may be on, the source of noise is the same. Note : modulation can not be imposed on this noise. D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------------------------------- NON |Voice 7|Voice 6|Voice 5|Voice 4|Voice 3|Voice 2|Voice 1|Voice 0| (3DH) ----------------------------------------------------------------- (4) EON Echo on/off. On with "1". D0-7 correspond to Voice0-7. D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------------------------------- EON |Voice 7|Voice 6|Voice 5|Voice 4|Voice 3|Voice 2|Voice 1|Voice 0| (4DH) ----------------------------------------------------------------- (5) FLG D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------------------------------- | | | ---- | NCK | FLG | RES | MUTE | ECEN | | | | | | (6CH) ----------------------------------------------------------------- RES: Soft reset is turned on when D7=1. At this time, all voices are in a state of "key on" suspension and Muted on. it becomes ="1" with power on. MUTE: Mute is turned on in all voices when D6 = 1. Becomes 1 with power on. ---- ECEN: Becomes possible to write into external memory through Echo. When D5=0. (Echo Enable). After power on. read out data is indeterminate until initial write in is carried out by the CPU. NCK: Designates the clock of the noise generator. Table 6.2.2. Noise Generator Clock ---------------------------------------------------------------- | NCK | Freq | NCK | Freq | NCK | Freq | NCK | Freq | ---------------------------------------------------------------- | 00 | 0 Hz | 08 | 83 | 10 | 500Hz | 18 | 3.2 | ---------------------------------------------------------------- | 01 | 16 | 09 | 100 | 11 | 667 | 19 | 4.0 | ---------------------------------------------------------------- | 02 | 21 | 0A | 125 | 12 | 800 | 1A | 5.3 | ---------------------------------------------------------------- | 03 | 25 | 0B | 107 | 13 | 1.0khz | 1B | 6.4 | ---------------------------------------------------------------- | 04 | 31 | 0C | 200 | 14 | 1.3 | 1C | 8.0 | ---------------------------------------------------------------- | 05 | 42 | 0D | 250 | 15 | 1.6 | 1D | 10.7 | ---------------------------------------------------------------- | 06 | 50 | 0E | 333 | 16 | 2.0 | 1E | 16 | ---------------------------------------------------------------- | 07 | 63 | 0F | 400 | 17 | 2.7 | 1F | 32 | ---------------------------------------------------------------- it is only possible to write into these registers from the CPU section. (6) ENDX When BRR decode of the block having the Source en flag is completed. the DSP section sets up a "1" 00-7 correspond to Voice0-7. If there is a voice which has been keyed on, the bit corresponding to this is reset. In addition, when the CPU section writes into this register, all bits are reset. D7 D6 D5 D4 D3 D2 D1 D0 ----------------------------------------------------------------- ENDX |Voice 7|Voice 6|Voice 5|Voice 4|Voice 3|Voice 2|Voice 1|Voice 0| (7CH) ----------------------------------------------------------------- (7) MVOL(L), MVOL(R), EVOL(L), EVOL(R) Refer to Main Volume (Lch, Rch). Echo Volume (Lch, Rch). Main volume (echo volume) of each channel is added to echo volume (main volume) and output. D7 D6 D5 D4 D3 D2 D1 D0 MVOL(Lch, Rch) ------------------------------------------- EVOL(Lch, Rch) | Sign | | | | | | | | (0CH) ------------------------------------------- (1CH) (8) ESA Echo Start Address, Issues the off-set address of the Echo region. [ESA] x 100H becomes the lead-off address of the Echo region. (9) EDL Echo Delay. Only the lower level four bits are operable. Delay time is an interval of 16msec, and is variable within a range of 0-240msec. If this time is considered to be 1, the necessary external memory region is (21)Kbytes (maximum 30Kbyte). However, when EDL = 0, the four-byte memory region of ESA -ESA+3 becomes necessary. D7 D6 D5 D4 D3 D2 D1 D0 EDL ----------------------------------------- (7DH) | -------------- | | | | | ----------------------------------------- (10) EFB Refers to Echo Feed-Back. Eight bits with sign. D7 D6 D5 D4 D3 D2 D1 D0 EFB ------------------------------------------- (0DH) | Sign | | | | | | | | ------------------------------------------- (11) DIR Issues the off-set address of the source directory. DIRx100 is the lead-off address of the directory. (DIRx100 or DIRxYYYY, I can't be sure, the picture isn't good ). (12) C0-C7 Issues the echo filter coefficient. Eight bits with sign. Makes up an eight tap FIR filter (filter identical with that of Lch. Rch.) D7 D6 D5 D4 D3 D2 D1 D0 C0-C7 ------------------------------------------- (0FH>-(7FH) | Sign | | | | | | | | ------------------------------------------- Filter Setting Example 1: when a low bass filter is imposed on the echo sound. ------------------------------- | Register | Numerical Value | ------------------------------- | C0 | FF | ------------------------------- | C1 | 08 | ------------------------------- | C2 | 17 | ------------------------------- | C3 | 24 | ------------------------------- | C4 | 24 | ------------------------------- | C5 | 17 | ------------------------------- | C6 | 08 | ------------------------------- | C7 | FF | ------------------------------- Filter Setting Example 2: When the echo sound is given the same tone color as the original sound. ------------------------------- | Register | Numerical Value | ------------------------------- | C0 | 7F | ------------------------------- | C1 | 00 | ------------------------------- | C2 | 00 | ------------------------------- | C3 | 00 | ------------------------------- | C4 | 00 | ------------------------------- | C5 | 00 | ------------------------------- | C6 | 00 | ------------------------------- | C7 | 00 | ------------------------------- 6.3. SOUND SOURCE DATA (SOURCE) SPECIFICATIONS. Sound source data is produced according to the following specifications by means of specialized tolls. 6.3.1. Source Directory (1) SA(H), SA(L) The source atari address, 16 bits, The address is the lead-off addres of the lead-off block. (2) LSA(H), LSA(L) Source loop start address 16 bits. The address is the lead-off of the loop start block. Table 5.3.1. source Directory ---------------------------- Memory Address | Directory | ---------------------------- n+0 | SA(L) | SA : Source Start Address n+1 | SA(H) | n+2 | LSA(L) | LSA : Source Loop Start Address n+3 | LDA(H) | ---------------------------- n = (DIR) x 100H + (SRCN)x4 A A A A 15 8 7 0 ------------------------------------- | DIR | 0 0 0 0 0 0 0 0 | ------------------------------------- | SRCN | 0 0 | --------------------------- +) -------------------------------------- -------------------------------------- | n | -------------------------------------- 6.3.2. SOURCE DATA (1) BLOCK FORMAT The sound, sampled at 32Khz, undergoes BRR (bit rate reduction) processing and the data is condensed from 16 bits to four bits. The four-bit data is arranged into sixteen portions an together with the RF register, is formed into one block of nine bytes. Table 6.3.2. Block Format. D7 D6 D5 D4 D3 D2 D1 D0 ------------------------------------------ RF | BRR DATA |Loop | END| | |on/off| | ------------------------------------------- D | D H | D L | A,0 | A,0 | A,0 | ------------------------------------------- D | D H | D L | H,0 | H,0 | H,0 | ------------------------------------------- D | D H | D L | A,1 | A,1 | A,1 | ------------------------------------------- D | D H | D L | H,1 | H,1 | H,1 | ------------------------------------------- D | D H | D L | A,2 | A,2 | A,2 | ------------------------------------------- D | D H | D L | H,2 | H,2 | H,2 | ------------------------------------------- D | D H | D L | A,3 | A,3 | A,3 | ------------------------------------------- D | D H | D L | H,3 | H,3 | H,3 | ------------------------------------------- D7-D2 is data relating to BRR. When D1=1 it indicates that it is a source having a loop, and when D0=1 it indicates that the block is the clock with the final data. 7. CPU ORGANIZATION. A Sony SPC700 series is used in the CPU core of the SFX sound source. it is possible to access and address space of 64K bytes in the SPC series CPU. Address classification of the memory space is made according to purpose: and addresses 0000 - 00ff are called page 0 and addresses 0100 - 01ff are called page 1. In regard to the data in this region, when direct page designation is carried out by direct page flaq (P) within the program status word, it is possible to carry out data processing in wide-ranging addresing modes with a small number of cycles. Within the CPU there are the universal registers A,X and Y, program status ward (PSW) of the varius flags, program counter (PC), and stack pointer (SP). The A register is operable by the greatest number of commands, and becomes and 8-bit operation accumulator. When 16-bit operations are carried out, it becomes paired with Y register and becomes the lower lever 8-bit register of the 16-bit accumulator. The X and Y registers, in addition to their function as universal registers, are used in various operations, such as the function as index register of various index addressing modes, the function as dual-address command source, destination address register, etc. In the command set there are single address commands which carry out arithmetic and logical operations centered in the A register and dual address commands which can designate random address within the direct page as source address and destination addresses. In regard to bit processing diversified by control purpose. Boolean bit operation commands are applicable to the 8K byte range of data of addresses 0000 - 1fff. Morever, in regard to the bits within the total space of the 64K bytes, commads of multiple bit test and set, test and reset are provided for. For the purpose of data which must be systematized or in order to carry out data processing rapidly. It is possible to operate 16-bit data with a single commad. Addition, subtraction, comparison and transferrance are possible between two byte of continuous 16-bit data within the direct page and the paired Y register and A register. In addition increment and decrement of continuous 16-bit data within the direct page are possible. There are multiplication and division commands for the purpose of rapid data processing and processing of data ina variety of forms. Multiplication is 8-bit x 8-bit with no sign and is carried out with the multiplicand stored in the Y register and the multiplier stored in the A register; the result is entered into the Y, A 16-bit accumulator. Division is 16bits/8bits with no sign and carried out with the divident stored in the Y, A 16 bit accumulator and the divisor stored in the X register : the resulting quotient is entered into the A register and the remainder is entered intro the Y register. In the processing of decimal data, there are decimal (addition, subtraction) correcting commands in regard to the results of both addition and subtraction. In regard to branched commands, there are relative branched commands according to the conditions of the various status flags, branched commands according to the conditions of set or reset of random bits with the direct page, etc. In addition, in regard to looped branched commands, there are comparision branched commands and subraction branched commands, and for these there are two types of addressing modes. In regard to subroutine call commands, there are subroutine address direct designation three-byte call commands within the 64K bytes. two-byte call commands for calling subroutines of specific areas, and 16 portion one-byte call commands using call table: it is possible to improve byte efficiency through proper useage in response to the frequency of subroutine use. 1. CPU REGISTERS Withing the CPU are the registers necessary for the execution of the various commands. These are an A register (note : functions as an 8-bit accumulator). X register, Y register (8-bit universal register which can also be used as index register). PSW ( program status ward). SP (stack pointer), etc. These are all 8-bit registersm but the PC (program counter) is made up of 16 bits. ------------------------------ P|C | Program Counter (16 bits) ------------------------------ ---------------- | A | A Register (8 bits) ---------------- ------------------------------ Y | A | (Y,A Paired 16-bit Acumulator) ------------------------------ (16 bits) ---------------- | X | X Register (8 bits) ---------------- ---------------- | Y | Y Register (8 bits) ---------------- ---------------- | SP | Stack Pointer (8 bits) ---------------- ---------------- | PSW | Program Status Ward (8 bits) ---------------- / / --------------- |N|V|P|-|H|-|Z|C| --------------- N = Negative Flag V = Overflow Flag P = Direct Page Flag H = Half Carry Flag Z = Zero Flag C = Carry Flag (Bit Accumulator) (1) A REGISTER This register is used as an 8-bit accumulator. At times of 16-bit operation commands. it becomes a register for retaining low byte data in the 16-bit accumulator made up of this paired with the Y register. When operation commands are issued, it becomes the multiplier register and low byte data of the product is entered. When divison commands are issued, paired with the Y register it formulates the dividend and the resulting quotient is entered. (2) X REGISTER In addition to its role as a universal data register, it also functions as an index register when index addressing is being carried out. In addition, it is also used as a two-address command destination address register and X register indirect address register. In division commands, it vecomes the divisor register. (3) Y REGISTER In additon to its role as a universal data register, it also functions as an index register when index addressing is being carried out, In addition, it is also used as a two-address command source address register. When carrying out 16-bit operation commands, it becomes the register which retains the high byte data of the 16-bit accumulator which is made up of the pairing of this with the A register. When multiplication commads are being carried out, it becomes the dividend register and the product high byte data is entered. When carrying out division commands, paired with the A register it formulates the dividend, and the resulting remained is entered. (4) PROGRAM COUNTER (PC) The program counter is made up of 16 bits and has an address region of 64K bytes. The upper level 8 bits are called PCH and the lower level 8 bits are referred to as PCL- Normally, it would have the address to be executed next and would be incremented only the number of bytes necessary fo the command fetched. When there is a branching commad in the oidst of the program the address of the branch destination would be stored in the program counter. When there is a reset (negative POR) input, reset vector which are in addresses FFFF and FFFE enter respectively PCH and PCL and branching takes place. (5) STACK POINTER (SP) The stack pointer is used to send data to RAM or to recover from RAM when subroutine call, push (PUSH), pop (POP), or return (RET) commands are being carried out. The address region indicated by the stack pointer is within page 1 (addresses 0100-01ff) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -------------------------------------- 0 0 0 0 0 0 0 1| SP Values | -------------------------------------- Fixed by Hardware Determined by the Program. When sending data to RAM, the stack pointer decreases by one after sending data (post decrement) and increases by one prior to restoring data (pre-increment). The diversified activites of the stack pointer are summarized below: SUB-ROUTINE CALLS -------------------------------------------------------- |Stack Address| Activity | SP Value after sending| -------------------------------------------------------- | SP | sending to PCH | SP-1 | | SP-1 | sending to PCL | SP-2 | -------------------------------------------------------- RESTORING FROM SUB-ROUTINE -------------------------------------------------------- |Stack Address| Activity | SP Value after sending| -------------------------------------------------------- | SP+1 | sending to PCH | SP+1 | | SP+1 | sending to PCL | SP+2 | -------------------------------------------------------- To send to A register, X register, Y register, PSW to and from the stack, the commands PUSH and POP can be used. PUSH A (X,Y, PSW) --------------------------------------------------------- |Stack Address| Activity | SP Value after sending| --------------------------------------------------------- | SP |sending of A (X..)| SP-1 | --------------------------------------------------------- POP A (X,Y, PSW) --------------------------------------------------------- |Stack Address| Activity | SP Value after sending| --------------------------------------------------------- | SP+1 |sending of A (X..)| SP+1 | --------------------------------------------------------- (6) PROGRAM STATUS WARD (PSW) The program status ward is made up of the various flags which are set and reset according to the results of the execution of 8-bit register commads and the various flags which determine the activities of the CPU. When reset it veocnes "000-0-00". 7 6 5 4 3 2 1 0 ----------------------------------------------- | N V P - H - Z C | ---------------------------------------------- Carry Flag (C). After operation execution, this is set when there has been a carry from the uppermost bit of the arithmetic logic unit (ALU) or when there has been no borrow. It is even altered with shift or rotate commands. It also acts as an bit accumulator of Boolean bit operation commands. It is set at the SETC commads and reset at the CLRC commads. In addition, the carry flag inverts at the NOTC commads. Zero Flag (Z) Alter operation execution, this flag is set when the result is zero and is reset whens the result is not zero. Even with 16-bity operation commands, zero detection is carried out. It is possible to carry out tests with conditional branching commands. Half Carry Flag (H) After operation execution, this flag is set when there has been a carry from form bit 3 of the ALU to bit 4, or when there has not been any borrow. There is no command to set, however, it is reset by reset by means of the CLRV commad. At his time, the overflow flag is also set. Direct Page Flag (P) This is the flaq which designates the direct page to which many addressing mode are applicable, such as direct page addressing etc. When 0, the direct page becomes the addresses of the region 0000-00ff and when 1, it becomes the addresses of the region 0100-01ff. It is set by the STEP command and reset by the CLRP command. Overflow Flag (V). After arithmetic operation execution, this flag is set when overflow or underflow has been produced. At this time, influence is extended simultaneously to the H flag. It is possible to carry out tests with conditional branching commads. Negative Flag (N) After operation execution, this flag is set when the values of the result of MSD is 1 and reset when that values is 0. It is possible to carry out tests with conditinal branching commads. 7.2. MEMORY SPACE. It is possible for the Sound-CPU to address 64K bytes of memory. Memory space is divide up according to purpose. From address 0000, 512 bytes are divided into two pages of 256-bytes units, called zero page and page one. It is possible to access data within these regions by means of numerous address modes, such as direct page addresing, etc. Page one is taken up by the stack. 7.2.1. Direct Pages (Zero Page, Page One) By means of setting or resetting the direct page (P) flag within the program status ward. it is possible to disignate whether zero page or page one is to be made the direct page. it is set up such that the data within this page can be treated with fewer bytes, at highter speed and with more numerous types of commands and addressing modes. Stack Area ---------- The stack region is established in the RAM region within page one. The uppermost byte of the stack address is fixed at 01. The lowermost byte of the stack address must be given its initial setting by the program. 7.2.2. Uppermost Page Internal ROM Region A mask ROM is installed within the Sound-CPU from FFC0H- FFFF. There is a program in it which transmits data from the ROM cassette to the 256K bit RAM throuh the SCPU. This region is used by means of reset. 7.2.3. Area of Applicable Bit Operation Commads. (i) The commads SET1 (set memory bit) and CLR1 (clear memory bit) are applicable to one-bit data with the direct page. (ii) The commands TSET1 (test and set bit) and TCLR1 ( test and clear bit) are applicable to the total 64K byte region. (iii) The Boolean operation commands (AND1, OR1, EOR1, MOV1, NOT1) are applicable to the 8K byte region of 0000 - 1FFF. Fig. 7.2.3. Region of Applicable Bit Operation Commands. ---------------------------------------------------------- 0000 | | | | | | | | | SET1, CLR1 | | AND1,OR1,EOR1, | | TSET1,TCLR1 | | | applicable | | MOV1,NOT1 | | | | | to direct | | | | | 00FF | | page. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 01FF | ------------- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1FFF | ------------------ | | | | | | | | | | | | | | | | | | | | 7FFF | ------------- | | | | | Unusuable | FFBF | | | FFC0 | ------------- | | | | | IPL-ROM | | | | FFFF | | | ---------------------------------------------------------- 7.2.4. Direct Page Addressing Since all of the addressing modes indicated in Table 7.2.4 are applicable to the data of the direct page (P=0: addresses 0000-00FF P=1: address 0000 - 01FF) designated by the direct page (P) flag. it is possible to manipulate the data in various ways. In additon byte efficiency also improves due to the fact that direct address designation is possible by one-byte data within the command words. Moreover, since effective commad cycles also decrease data can be accessed more rapidly. Table 7.2.4. Memory Access Addressing Effective Address -------------------------------------------------------------------- #of Effective Addr. Region Simbol | Addressing Bytes 0000-01FF 1FFF 1FFF -------------------------------------------------------------------- dp Direct Page 2 X X dp+X X-Indexed Direct Page 2 X X dp+Y Y-Indexed Direct Page 2 X X (X) Indirect 1 X X (X)+ Indirect Auto-increment 1 X X dp,dp Direct Page to D.P. 3 X X (X),(Y) Indirect Page to I.P. 1 X X dp Inm Inmediate Data to D.P. 3 X X dp, bit Direct Page Bit 2 X X dp,bit,rel Direct Page Bit Relative 3 X X mem, bit Absolute Boolean Bit 3 X X labs Absolute 3 X X X labs+X X-indexed Absolute 3 X X X labs+Y Y-indexed Absolute 3 X X X (dp+X) X-indexed Indirect 2 X X X (dp)+Y Indirect Y-indexed Indirect 2 X X X -------------------------------------------------------------------- 9. SUMMARY OF SPC700 COMMANDS. An SPC700 series is used for the SFX sound source CPU. However, standby and sleep modes can not be used. The command set operand notation and explanation of command activity are indicated in the table below. The upper portion of the table are symbols necesary to operand description. These are symbols necessary assembler description. In the lower portion of the table, the values of the various operand are expressed as symbols. Assembler descriptions are given as numerical values or labels. Table 9.1. Command Operand Symbols and Meaning Symbol ----------------------------------------------- A A register X X register Y Y register PSW Program status ward YA Y, A paired 16-bit register PC Program counter SP Stack pointer ( ) Indirect expression ( )+ Indirect auto-increment expression # Inmediate data | Absolute address / Bit reversal . Bit position indicator ( ) Indexed Indirect expression H Hexadecial notation ------------------------------------------------ inm 8-bit inmediate data dp Offset address within direct page abs 16-bit absolute address rel Relative offset complement value of 2 mem Boolean bit operation address bit Bit location MSB X ----------------------- | | | |0| | | ----------------------- \----X----/ MSB Y ----------------------- | | | |0| | | ----------------------- \----Y----/ upage Offset within U page n Vector call number. In giving an explanation of opertaions, in addition to the notations and simbols above, the following symbols are also used. Table 9.2. Symbols and Meaning of Operation Explanation Symbol Meaging --------------------------------------- N Negative flag V Overflow flag P Direct page flag B Break flag H Half carry flag I Indirect master enable flag Z Zero flag C Carry flag + Addition - Subtraction : Comparison AND Logic product OR Logic sun EOR Exclusive logic sun * Multiplication / Division Q Division quotient R Division remainer (d) Destination (S) Source --- Direction of data transmision - - Data decrement + + Data increment < < 1 bit shift left > > 1 bit shift right ------------------------------ Note : The number of cycles of conditional branching commands are appreorite to cases when there is no branching to the left side and when theree is branching tothe right side. Table 9.3. Explanation of Symbols in the Status Flag Column ----------------------------------------------- Symbol Meaning ----------------------------------------------- . No change 0 Cleared to 0 1 Set to 1 Flag name Set or cleared depending on result ----------------------------------------------- 1. 8-bit Data Transmission Commands. Group I ------------------------------------------------------------------------ Mnemonic Operand Code Bytes Cycles Operation Flag ------------------------------------------------------------------------ MOV A, #inm E8 2 2 A <- inm N......Z MOV A, (X) E6 1 3 A <- (X) N......Z MOV A, (X)+ BF 1 4 A <- (X) with auto inc N......Z MOV A, dp E4 2 3 A <- (dp) N......Z MOV A, dp+X F4 2 4 A <- (dp+X) N......Z MOV A, labs E5 3 4 A <- (abs) N......Z MOV A, labs+X F5 3 5 A <- (abs+X) N......Z MOV A, labs+Y F6 3 5 A <- (abs+Y) N......Z MOV A, (dp+X) E7 2 6 A <- ((dp+X+1)(dp+X)) N......Z MOV A, (dp)+Y F7 2 6 A <- ((dp+1)(dp)+Y) N......Z MOV X, #inm CD 2 2 X <- inm N......Z MOV X, dp F8 2 3 X <- (dp) N......Z MOV X, dp+Y F9 2 4 X <- (dp+Y) N......Z MOV X, labs E9 3 4 X <- (abs) N......Z MOV Y, #inm 8D 2 2 Y <- inm N......Z MOV Y, dp EB 2 3 Y <- (dp) N......Z MOV Y, dp+X FB 2 4 Y <- (dp+X) N......Z MOV Y, labs EC 3 4 Y <- (abs) N......Z ------------------------------------------------------------------------ 2. 8-BIT DATA TRANSMISSION COMMANDS. GROUP 2. ------------------------------------------------------------------------ Mnemonic Operand Code Bytes Cycles Operation Flag ------------------------------------------------------------------------ MOV (X),A C6 1 4 A -> (X) ........ MOV (X)+,A AF 1 4 A -> (X) with auto inc ........ MOV dp,A C4 2 4 A -> (dp) ........ MOV dp+X,A D4 2 5 A -> (dp+X) ........ MOV labs,A C5 3 5 A -> (abs) ........ MOV labs+X,A D5 3 6 A -> (abs+X) ........ MOV labs+Y,A D6 3 6 A -> (abs+Y) ........ MOV (dp+X),A C7 2 7 A -> ((dp+X+1)(dp+X)) ........ MOV (dp)+Y,A D7 2 7 A -> ((dp+1)(dp)+Y) ........ MOV dp,X D8 2 4 X -> (dp) ........ MOV dp+Y,X D9 2 5 X -> (dp+Y) ........ MOV labs,X C9 3 5 X -> (abs) ........ MOV dp,Y CB 2 4 X -> (dp) ........ MOV dp+X,Y DB 2 5 X -> (dp+X) ........ MOV labs,Y CC 3 5 X -> (abs) ........ ------------------------------------------------------------------------ 3. 8-BIT DATA TRANSMISSIN COMMANDS, GROUP 3. ------------------------------------------------------------------------ Mnemonic Operand Code Bytes Cycles Operation Flag ------------------------------------------------------------------------ MOV A, X 7D 1 2 A <- X N......Z MOV A, Y DD 1 2 A <- Y N......Z MOV X, A 5D 1 2 X <- A N......Z MOV Y, A FD 1 2 Y <- A N......Z MOV X, SP 9D 1 2 X <- SP N......Z MOV SP, X BD 1 2 SP <- X ........ MOV dp(d),dp(s) FA 3 5 (dp(d)) <- (dp(s)) ........ MOV dp,#inm 8F 3 5 (dp) <- inm ........ ------------------------------------------------------------------------ 4. 8-BIT ARITHMETIC OPERATION COMMANDS. ------------------------------------------------------------------------ Mnemonic Operand Code Bytes Cycles Operation Flag ------------------------------------------------------------------------ ADC A,#inm 88 2 2 A <- A+inm+C NV..H..ZC ADC A,(X) 86 1 3 A <- A+(X)+C NV..H..ZC ADC A,dp 84 2 3 A <- A+(dp)+C NV..H..ZC ADC A,dp+X 94 2 4 A <- A+(dp+X)+C NV..H..ZC ADC A,labs 85 3 4 A <- A+(abs)+C NV..H..ZC ADC A,labs+X 95 3 5 A <- A+(abs+X)+C NV..H..ZC ADC A,labs+Y 96 3 5 A <- A+(abs+Y)+C NV..H..ZC ADC A,(dp+X) 87 2 6 A <- A+((dp+X+1)(dp+X)) NV..H..ZC ADC A,(dp)+Y 97 2 6 A <- A+((dp+1)(dp)+Y) NV..H..ZC ADC (X),(Y) 99 1 5 (X) <- (X)+(Y)+C NV..H..ZC ADC dp(d),dp(s) 89 3 6 (dp(d))<-(dp(d))+(dp(s))+C NV..H..ZC ADC dp,#inm 98 3 5 (dp) <- (dp)+inm+C NV..H..ZC ------------------------------------------------------------------------ SBC A,#inm A8 2 2 A <- A-inm-!C NV..H..ZC SBC A,(X) A6 1 3 A <- A-(X)-!C NV..H..ZC SBC A,dp A4 2 3 A <- A-(dp)-!C NV..H..ZC SBC A,dp+X B4 2 4 A <- A-(dp+X)-!C NV..H..ZC SBC A,labs A5 3 4 A <- A-(abs)-!C NV..H..ZC SBC A,labs+X B5 3 5 A <- A-(abs+X)-!C NV..H..ZC SBC A,labs+Y B6 3 5 A <- A-(abs+Y)-!C NV..H..ZC SBC A,(dp+X) A7 2 6 A <- A-((dp+X+1)(dp+X))-!C NV..H..ZC SBC A,(dp)+Y B7 2 6 A <- A-((dp+1)(dp)+Y)-!C NV..H..ZC SBC (X),(Y) B9 1 5 (X) <- (X)-(Y)-!C NV..H..ZC SBC dp(d),dp(s) A9 3 6 (dp(d))<-(dp(d))-(dp(s))-!C NV..H..ZC SBC dp,#inm B8 3 5 (dp) <- (dp)-inm-!C NV..H..ZC ------------------------------------------------------------------------ CMP A,#inm 68 2 2 A-inm N......ZC CMP A,(X) 66 1 3 A-(X) N......ZC CMP A,dp 64 2 3 A-(dp) N......ZC CMP A,dp+X 74 2 4 A-(dp+X) N......ZC CMP A,labs 65 3 4 A-(abs) N......ZC CMP A,labs+X 75 3 5 A-(abs+X) N......ZC CMP A,labs+Y 76 3 5 A-(abs+Y) N......ZC CMP A,(dp+X) 67 2 6 A-((dp+X+1)(dp+X)) N......ZC CMP A,(dp)+Y 77 2 6 A-((dp+1)(dp)+Y) N......ZC CMP (X),(Y) 79 1 5 (X)-(Y) N......ZC CMP dp(d),dp(s) 69 3 6 (dp(d))-(dp(s)) N......ZC CMP dp,#inm 78 3 5 (dp)-inm N......ZC CMP X,#inm C8 2 2 X-inm N......ZC CMP X,dp 3E 2 3 X-(dp) N......ZC CMP X,labs 1E 3 4 X-(abs) N......ZC CMP Y,#inm AD 2 2 Y-inm N......ZC CMP Y,dp 7E 2 3 Y-(dp) N......ZC CMP Y,labs 5E 3 4 Y-(abs) N......ZC ------------------------------------------------------------------------ 5. 8-BIT LOGIC OPERATION COMMANDS. ------------------------------------------------------------------------ Mnemonic Operand Code Bytes Cycles Operation Flag ------------------------------------------------------------------------ AND A,#inm 28 2 2 A <- A AND inm N......Z. AND A,(X) 26 1 3 A <- A AND (X) N......Z. AND A,dp 24 2 3 A <- A AND (dp) N......Z. AND A,dp+X 34 2 4 A <- A AND (dp+X) N......Z. AND A,labs 25 3 4 A <- A AND (abs) N......Z. AND A,labs+X 35 3 5 A <- A AND (abs+X) N......Z. AND A,labs+Y 36 3 5 A <- A AND (abs+Y) N......Z. AND A,(dp+X) 27 2 6 A <- A AND ((dp+X+1)(dp+X)) N......Z. AND A,(dp)+Y 37 2 6 A <- A AND ((dp+1)(dp)+Y) N......Z. AND (X),(Y) 39 1 5 (X) <- (X) AND (Y) N......Z. AND dp(d),dp(s) 29 3 6 (dp(d))<-(dp(d)) AND (dp(s)) N......Z. AND dp,#inm 38 3 5 (dp) <- (dp) AND inm N......Z. ------------------------------------------------------------------------ OR A,#inm 08 2 2 A <- A OR inm N......Z. OR A,(X) 06 1 3 A <- A OR (X) N......Z. OR A,dp 04 2 3 A <- A OR (dp) N......Z. OR A,dp+X 14 2 4 A <- A OR (dp+X) N......Z. OR A,labs 05 3 4 A <- A OR (abs) N......Z. OR A,labs+X 15 3 5 A <- A OR (abs+X) N......Z. OR A,labs+Y 16 3 5 A <- A OR (abs+Y) N......Z. OR A,(dp+X) 07 2 6 A <- A OR ((dp+X+1)(dp+X)) N......Z. OR A,(dp)+Y 17 2 6 A <- A OR ((dp+1)(dp)+Y) N......Z. OR (X),(Y) 19 1 5 (X) <- (X) OR (Y) N......Z. OR dp(d),dp(s) 09 3 6 (dp(d))<-(dp(d)) OR (dp(s)) N......Z. OR dp,#inm 18 3 5 (dp) <- (dp) OR inm N......Z. ------------------------------------------------------------------------ EOR A,#inm 48 2 2 A <- A EOR inm N......Z. EOR A,(X) 46 1 3 A <- A EOR (X) N......Z. EOR A,dp 44 2 3 A <- A EOR (dp) N......Z. EOR A,dp+X 54 2 4 A <- A EOR (dp+X) N......Z. EOR A,labs 45 3 4 A <- A EOR (abs) N......Z. EOR A,labs+X 55 3 5 A <- A EOR (abs+X) N......Z. EOR A,labs+Y 56 3 5 A <- A EOR (abs+Y) N......Z. EOR A,(dp+X) 47 2 6 A <- A EOR ((dp+X+1)(dp+X)) N......Z. EOR A,(dp)+Y 57 2 6 A <- A EOR ((dp+1)(dp)+Y) N......Z. EOR (X),(Y) 59 1 5 (X) <- (X) EOR (Y) N......Z. EOR dp(d),dp(s) 49 3 6 (dp(d))<-(dp(d)) EOR (dp(s)) N......Z. EOR dp,#inm 58 3 5 (dp) <- (dp) EOR inm N......Z. ------------------------------------------------------------------------ 6. ADDITION & SUBTRACTION COMMANDS. ------------------------------------------------------------------------ Mnemonic Operand Code Bytes Cycles Operation Flag ------------------------------------------------------------------------ INC A BC 1 2 ++ A N......Z. INC dp AB 2 4 ++ (dp) N......Z. INC dp+X BB 2 5 ++ (dp+X) N......Z. INC labs AC 3 5 ++ (abs) N......Z. INC X 3D 1 2 ++ X N......Z. INC Y FC 1 2 ++ Y N......Z. ----------------------------------------------------------------------- DEC A 9C 1 2 -- A N......Z. DEC dp 8B 2 4 -- (dp) N......Z. DEC dp+X 9B 2 5 -- (dp+X) N......Z. DEC labs 8C 3 5 -- (abs) N......Z. DEC X 1D 1 2 -- X N......Z. DEC Y DC 1 2 -- Y N......Z. ----------------------------------------------------------------------- 7. SHIFT, ROTATION COMMANDS ------------------------------------------------------------------------ Mnemonic Operand Code Bytes Cycles Operation Flag ------------------------------------------------------------------------ ASL A 1C 1 2 C << A <<0 N......ZC ASL dp 0B 2 4 C << (dp) <<0 N......ZC ASL dp+X 1B 2 5 C << (dp+X) <<0 N......ZC ASL labs CC 3 5 C << (abs) <<0 N......ZC ----------------------------------------------------------------------- LSR A 5C 1 2 0 >> A <> (dp) <> (dp+X) <> (abs) <> A <> (dp) <> (dp+X) <> (abs) < A(3-0) N......Z. ----------------------------------------------------------------------- 8. 16-BIT TRANSMISION COMMANDS ------------------------------------------------------------------------ Mnemonic Operand Code Bytes Cycles Operation Flag ------------------------------------------------------------------------ MOVW YA,dp BA 2 5 YA - (dp+1)(dp) N......Z. MOVW dp,YA DA 2 4 (dp+1)(dp) - YA ......... ----------------------------------------------------------------------- 9. 16-BIT OPERATION COMMANDS. ----------------------------------------------------------------------- Mnemonic Operand Code Bytes Cycles Operation Flag ----------------------------------------------------------------------- INCW dp 3A 2 6 Increment dp memory pair N......Z. DECW dp 1A 2 6 Decrement dp memory pair N......Z. ADDW YA,dp 7A 2 5 YA <- YA + (dp+1)(dp) NV..H..ZC SUBW YA,dp 9A 2 5 YA <- YA - (dp+1)(dp) NV..H..ZC CMPW YA,dp 5A 2 4 YA - (dp+1)(dp) N......Z. ----------------------------------------------------------------------- 10. MULTIPLICATION & DIVISON COMMANDS. ----------------------------------------------------------------------- Mnemonic Operand Code Bytes Cycles Operation Flag ----------------------------------------------------------------------- MUL YA CF 1 9 YA(16 bits) <- Y * A N......Z. DIV YA,X 9E 1 12 Q:A B:Y <- YA / X NV..H..Z. ----------------------------------------------------------------------- 11. DECIMAL COMPENSATION COMMANDS. ----------------------------------------------------------------------- Mnemonic Operand Code Bytes Cycles Operation Flag ----------------------------------------------------------------------- DAA A DF 1 3 decimal adjust for add N......ZC DAS A BE 1 3 decimal adjust for sub N......ZC ----------------------------------------------------------------------- 12. BRANCHING COMMANDS. ----------------------------------------------------------------------- Mnemonic Operand Code Bytes Cycles Operation Flag ----------------------------------------------------------------------- BRA rel 2F 2 4 branch always ... BEQ rel F0 2 2/4 branch on Z=1 ... BNE rel D0 2 2/4 branch on Z=0 ... BCS rel B0 2 2/4 branch on C=1 ... BCC rel 90 2 2/4 branch on C=0 ... BVS rel 70 2 2/4 branch on V=1 ... BVC rel 50 2 2/4 branch on V=0 ... BMI rel 30 2 2/4 branch on N=1 ... BPL rel 10 2 2/4 branch on N=0 ... BBS dp.bit,rel x3 3 5/7 branch on dp.bit=1 ... BBC dp.bit,rel y3 3 5/7 branch on dp.bit=0 ... CBNE dp,rel 2E 3 5/7 compare A with (dp) then BNE ... CBNE dp+X,rel DE 3 6/8 compare A with (dp+X) then BNE ... DBNZ dp,rel 6E 3 5/7 decrement memory (dp) then JNZ ... DBNZ Y,rel FE 2 4/6 decrement Y then JNZ ... JMP labs 5F 3 3 jump to new location ... JMP (labs+X) 1F 3 6 PC <- (abs+X+1)(abs+X) ... ----------------------------------------------------------------------- 13. SUB-ROUTINE CALL RETURN COMMANDS. ----------------------------------------------------------------------- Mnemonic Operand Code Bytes Cycles Operation NVPBHIZC ----------------------------------------------------------------------- CALL labs 3F 3 8 subroutine call ........ PCALL upage 4F 2 6 upage call ........ TCALL n n1 1 8 table call ........ BRK 0F 1 8 software interrupt ...1.0.. RET 6F 1 5 return from subroutine ........ RET1 7F 1 6 return from interrupt (Restored) ----------------------------------------------------------------------- 14. STACK OPERATION COMMANDS. ----------------------------------------------------------------------- Mnemonic Operand Code Bytes Cycles Operation Flag ----------------------------------------------------------------------- PUSH A 2D 1 4 push A to stack ......... PUSH X 4D 1 4 push X to stack ......... PUSH Y 6D 1 4 push Y to stack ......... PUSH PSW 0D 1 4 push PSW to stack ......... ----------------------------------------------------------------------- POP A AE 1 4 pop A from stack ......... POP X CE 1 4 pop X from stack ......... POP Y EE 1 4 pop Y from stack ......... POP PSW 8E 1 4 pop PSW from stack (Restored) ----------------------------------------------------------------------- 15. BIT OPERATION COMMANDS. ----------------------------------------------------------------------- Mnemonic Operand Code Bytes Cycles Operation Flag ----------------------------------------------------------------------- SET1 dip.bit x2 2 4 set direct page bit ......... CLR1 dip.bit y2 2 4 clear direct page bit ......... TSET1 labs 0E 3 6 test and set bits with A N......Z. TCLR1 labs 4E 3 6 test and clear bits with A N......Z. AND1 C,mem.bit 4A 3 4 C <- C AND (mem.bit) ........C AND1 C,/mem.bit 6A 3 4 C <- C AND !(mem.bit) ........C OR1 C,mem.bit 0A 3 5 C <- C OR (mem.bit) ........C OR1 C,/mem.bit 2A 3 5 C <- C OR !(mem.bit) ........C EOR1 C,mem.bit 8A 3 5 C <- C EOR (mem.bit) ........C NOT1 mem.bit EA 3 5 complement (mem.bit) ......... MOV1 C,mem.bit AA 3 4 C <- (mem.bit) ........C MOV1 mem.bit,C CA 3 6 C -> (mem.bit) ......... ----------------------------------------------------------------------- 16. PROGRAM STATUS FLAG OPERATION COMMANDS. ----------------------------------------------------------------------- Mnemonic Operand Code Bytes Cycles Operation NVPBHIZC ----------------------------------------------------------------------- CLRC 60 1 2 clear carry flag .......0 SETC 80 1 2 set carry flag .......1 NOTC ED 1 3 complement carry flag .......C CLRV E0 1 2 clear V and H .0..0... CLRP 20 1 2 clear direct page flag ..0..... SETP 40 1 2 set dorect page flag ..1..0.. EI A0 1 3 set interrup enable flag .....1.. DI C0 1 3 clear interrup enable flag .....0.. ----------------------------------------------------------------------- 17. OTHER COMMANDS. ----------------------------------------------------------------------- Mnemonic Operand Code Bytes Cycles Operation Flag ----------------------------------------------------------------------- NOP 00 1 2 no operation ......... SLEEP EF 1 3 standby SLEEP mode ......... STOP FF 1 3 standby STOP mode ......... ----------------------------------------------------------------------- docs/spc_file_format.txt0000755000000000000000000001056311266514606012610 0ustar SPC File Format v0.30 ===================== Offset Size Description ------ ----- ------------------------------------------------------------------ 00000h 33 File header "SNES-SPC700 Sound File Data v0.30" 00021h 2 26,26 00023h 1 26 = header contains ID666 information 27 = header contains no ID666 tag 00024h 1 Version minor (i.e. 30) SPC700 Registers: 00025h 2 PC 00027h 1 A 00028h 1 X 00029h 1 Y 0002Ah 1 PSW 0002Bh 1 SP (lower byte) 0002Ch 3 reserved ID666 Tag (text format): 0002Eh 32 Song title 0004Eh 32 Game title 0006Eh 16 Name of dumper 0007Eh 32 Comments 0009Eh 11 Date SPC was dumped (MM/DD/YYYY) 000A9h 3 Number of seconds to play song before fading out 000ACh 5 Length of fade in milliseconds 000B1h 32 Artist of song 000D1h 1 Default channel disables (0 = enable, 1 = disable) 000D2h 1 Emulator used to dump SPC: 0 = unknown 1 = ZSNES 2 = Snes9x 000D3h 45 reserved (set to all 0's) ID666 Tag (binary format): 0002Eh 32 Song title 0004Eh 32 Game title 0006Eh 16 Name of dumper 0007Eh 32 Comments 0009Eh 4 Date SPC was dumped (YYYYMMDD) 000A2h 7 unused 000A9h 3 Number of seconds to play song before fading out 000ACh 4 Length of fade in milliseconds 000B0h 32 Artist of song 000D0h 1 Default channel disables (0 = enable, 1 = disable) 000D1h 1 Emulator used to dump SPC: 0 = unknown 1 = ZSNES 2 = Snes9x 000D2h 46 reserved (set to all 0's) 00100h 65536 64KB RAM 10100h 128 DSP Registers 10180h 64 unused 101C0h 64 Extra RAM (Memory region used when the IPL ROM region is set to read-only) Extended ID666 Format ===================== Extended information is stored at the end of the SPC file as an IFF chunk with an ID of "xid6". Items that can be stored in the ID666 tag without any loss of data should not be stored in the extended area. Offset Size Description ------ ---- ------------------------------------------------------------------ 0 4 Chunk type "xid6" 4 4 Chunk size, not including header Sub-chunk Header ---------------- Inside the chunk are sub-chunks. Each sub-chunk consists of a 4-byte header, and possibly data. All data is 32-bit aligned. If the data stored doesn't reach a 32-bit boundary, it will be padded with 0's. Offset Size Description ------ ---- ------------------------------------------------------------------ 0 1 ID - song name, length, etc. 1 1 Type - 0 means data is stored in the header non-zero means data is stored after header 2 2 Data - if 'type' is non-zero, this contains the length of the following data Extended ID666 Items -------------------- ID: 00-0F - Items from original ID666 tag 10-1F - Extended items 30-3F - Items related to playback Type: Data - 'type' contains a 0, and data is saved in the 'data' item of the sub-chunk header. String - Data is stored as a null terminated string (max 256 characters including null). Currently, strings saved in SNESAmp use ANSI characters. However, support for UNICODE may be added. Integer - Data is stored as an integer Size: The minimum and maximum sizes of an item ID Type Size Description --- ------- ----- ------------------------------------------------------------ 01h String 4-256 Song name 02h String 4-256 Game name 03h String 4-256 Artist's name 04h String 4-256 Dumper's name 05h Integer 4 Date song was dumped (stored as yyyymmdd) 06h Data 1 Emulator used 07h String 4-256 Comments 10h String 4-256 Official Soundtrack Title 11h Data 1 OST disc 12h Data 2 OST track (upper byte is the number 0-99, lower byte is an optional ASCII character) 13h String 4-256 Publisher's name 14h Data 2 Copyright year 30h Integer 4 Introduction length (lengths are stored in 1/64000th seconds) 31h Integer 4 Loop length 32h Integer 4 End length 33h Integer 4 Fade length 34h Data 1 Muted channels (a bit is set for each channel that's muted) This may seem like a messy way to implement a format, but I wanted to assure something that would be easily expandible. docs/tasm700.zip0000755000000000000000000001153311266514607010631 0ustar PK ^HZC# TASM700.TABMs6@K1)~9$ƭ,bK&3qbI"BZ||xw>\ۺ"!otGs|j} >\WZyQGٯ]^|z)no>۫w_muu }yp$:-7u~f[oT#îFz%^ڝt ?/o. wf у90?昅уE[N|V~ ht>45K[9  &\PEBVNTpA^0.(8(LmrPs(z(y|-_ F}T da9+ &NZ9u# u# uxV9 Yȉ u(Â:H8(ArP@(AR.Hl: ]0v bzT Yʉ . ư1)5( 2WtAL`B K R .HiL( A ` \qPpArPsL( +yEd & lm7gUDؗ~ZFto/%*`/a0Z+:Q(`IQAQ1*,sPQ{iˁWNbZ6%ԮQjE)QTF^J}jۄV(]jE -aD_§mSus[3ۛ+{ui_HIm.+J畈r4ڿf^Y.tv53\6PR:&Q]-kɮ'f)b8A}_|h;{^h.0#G`λim*څ׋,!j8I*?OCFt˃:S.(WW)Γ!np8rDzuvU1k9p^̣VW 5y>hwԅ:c94<&~_ȺJat>gOM&4!נ⿘E(seN"QB*ʋA)wh4ʘ m+7V%s?ICΙ6i:՜&٤!xY8;9k:^J]40ʆec0K(5Z6G,'TP;Fv~K̀ɔk!:Vؒ xN[qބv`9pN0IzR$$%%(oA zJ9%TIAcj+(6׶.сRkk:k:\ӁV=Xfrc}<L:v`M v͆yY'Q$5sb2F*cklU%~"^ݩlkr3u J5&/ )WZgfq=Ţz[dhs捙Zު?BjmJ3 f-~LPc/xZAc/,2`80tP .ñ =~/ !0lB-9(P q QD]wE0u *a9 X(üscYy'yȂ`ZmtP- #+\<|Gx0w_'_Hf6pfd>uxP|D Ay՞gU?FuܞgQ>n1-{%"59|G=Nj԰ZU}K{R)_u(XP)o%+(zE^jՑNQXQu Q n…(^+b5(a2xQT;DCT=X\/k|&B"1@ İQw% P@b&<;zC?SVqYxV u)mHo62mFly(F5*H*.3C ǭI Fa =v\a3z!?Esğ0 VO41 R| )p$"N|}X7#v:8֞m*9ivb7DX~sĕoTmG `g7T_~{y,=tJw!Nm6w1]|o̧_~^$ߠ1|~d{jGEw3晘9xPTށ~+>%^|Vn2Je6};0ML&.̾1KE׆/e3]nB`馬֫zm"o~!+nY{[d[V~w ^./ʯ'V35@,IDmq C^J<@C\%2L[8?PK ^HZC#  TASM700.TABPKH w A  (SPC_CODE.ASMPK Uļ:  aREADME.TXTPKdocs/techspec.txt0000755000000000000000000001304111266514610011237 0ustar Version 1.0 Corsair + Kari presents the first doc of Fami hardware register locations and brief explanation of them.. If you would like to add any info found in this list please leave a mail message to Corsair or RamRaider on GRAVEYARD BBS +44-91-5160560 or anything to do with the FAMICON/SNES.. We have an INTERNET address if ya want it leave true e-mail! Or better still if ya can get the Programmers handbook (Both) please call and leave mail :) , or even the 100,000 quid SCSI SNASM board for FAMICON development :) Also if you want more info contact us the same way.. We are esp looking for contacts to help get to grips with this new platform everybody welcome! Special greetings to Starr/QUARTEX and any other True Console Dude! Memory Map ~~~~~~~~~~ Bank Address ~~~~ ~~~~~~~ 00- 0000-1fff Lo RAM (same as at $7e0000-$7e1fff) 7d 2100-2142(?) Videochip Registers 4300-437f DMA Registers 8000-ffff ROM:This contains 32k block of game ROM. So, the games are divided to 32k chunks which locate always at address $8000-$ffff, but in different banks. This means that the first 32k of game is at $008000-$00ffff and next 32k is at $018000-$01ffff etc. 7e 0000-1fff Lo RAM (same as always at $0000-$1fff) \ 2000-ffff RAM \ I'm not sure about } 128k RAM?? 7f 0000-ffff RAM / this RAM / 7f-ff all Not used??? $ffec($fffc) contains reset vector and $ffea($fffa) is NMI vector. The NMI is actually vertical blank interrupt. Video Chip ~~~~~~~~~~ size loc. ~~~~ ~~~~ B 2100 Screen fade x000bbbb x=screen on/off b=brightness(0-f) B 2106 Screen Pixelation xxxxbbbb x=pixel size b=planes to expand B 2107 Plane 0 location in vram xxxxxxab x=address ab=32/64 width xy B 2108 Plane 1 location in vram xxxxxxab as above B 2109 Plane 2 location in vram xxxxxxab as above B 210a Plane 3 location in vram xxxxxxab as above B 210b Tile VRAM address aaaabbbb a=Playfield 0 b=Playfield 1 B 210c Tile VRAM address ccccdddd c=Playfield 2 d=Playfield 3 2B 210d Plane 0 scroll x 8+3 bits (0-7ff) put first 8 bits and then 2B 210e Plane 0 scroll y 8+3 bits (0-7ff) 3 highest bits 2B 210f Plane 1 scroll x as above 2B 2110 Plane 1 scroll y as above 2B 2111 Plane 2 scroll x as above 2B 2112 Plane 2 scroll y as above 2B 2113 Plane 3 scroll x as above 2B 2114 Plane 3 scroll y as above B 2115 Video port control W 2116 Video port address (lo-hi) W 2118 Video port data (lo-hi) (address is incremented by 2) B 2121 Palette color nr B 2122 Palette color data B 212C Playfield Enable xxxxabcd a-d = playfield number.. B 2133 Screen mode 0000ab0c a=Interlace Y b=Overscan c=Interlace X?? 2140-2142 Audio Registers???? I/O ~~~ W B 420b Start dma (enable bits) bits: 76543210 = dma nr (8 DMA's) R B 4212 Pad ready to be read R W 4218 Pad 0 data 76543210 = A-B-Select-Start-U-D-L-R 4219 76543210 = X-Y-Top Left-Top Right-0000 R W 421a Pad 1 data as above R W 421c Pad 2 data as above R W 421e Pad 3 data as above DMA registers ($4300-$437f) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ B 43X0 DMA control reg??(not sure!) B 43X1 DMA destination (Access only to some of the video chip registers ($2100-$21ff) $18=video port $22=color palette W 43X2 Source address lo-hi 16 lowest bits B 43X4 Source Bank addr. 8 highest bits W 43X5 Transfer size lo-hi X=dma number (0-7) DMA #0= 4300-4305 DMA #1= 4310-4315 ... DMA #7= 4370-4375 Symbols: size: B=byte long 2B=put 2 bytes W=word long R=read only W=write only Screen Details ~~~~~~~~~~~~~~ Famicom Tile format is simple. Each Tile is 4 planes and 8x8 bits. 32 bytes are used per Tile . PLANES 1 & 2 PLANES 3 & 4 byte0 byte1 byte 16 byte 17 byte2 byte3 byte 18 byte 19 byte4 byte5 byte 20 byte 21 ..... ....... byte14 byte15 byte 30 byte 31 Screen Map ~~~~~~~~~~ Famicom can use only Tiles $0-$3ff, max 1024 chars. 16 bits: YX?c ccNN NNNN NNNN fedc ba98 7654 3210 Y = mirror y X = mirror x ?=unknown ccc = palette nr (8 palettes) NN.. = character number Screen Resolution is normally 32x30 - 64 bytes / line Screen VRAM Location ~~~~~~~~~~~~~~~~~~~~ Screen Width 32x32 offset for x,y 0,0 = 0 Screen Width 64x32 offset for x,y 0,0 = 0 33,0 = $400 Screen Width 32x60 offset for x,y 0,0 = 0 0,31 = $400 Screen Width 64x60 offset for x,y 0,0 = 0 33,0 = $400 0,31 = $800 33,31 = $c00 As can be seen if a wider mode is selected the extra height/width follow after the main screen in memory.